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ac 97 soundmax codec AD1986 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features ac `97 2.3 compliant features 6 dac channels for 5.1 surround s/pdif output integrated headphone amplifiers variable rate audio double rate audio (f s = 96 khz) greater than 90 db dynamic range 20-bit resolution on all dacs 20-bit resolution on all adcs line-level mono phone input high quality cd input selectable mic input w/preamp aux and line-in stereo inputs external amplifier power down (eapd) power management modes jack sensing and device identification 48-pin lqfp package enhanced features integrated parametric equalizer stereo microphone with up to 30 db gain boost integrated pll for system clocking variable sample rate: 7 khz to 96 khz 7 khz to 48 khz in 1 hz increments 96 khz for double rate audio jack sense with auto topology switching jack presence detection on up to 8 jacks three software-controlled vref_out signals software-enabled outputs for jack sharing auto-down mix and channel spreading microphone-to-mono output stereo microphone pass-through to mixer built-in microphone/center/lfe/line-in sharing built-in surround/line_in sharing center/lfe line swapping microphone swapping reduced support component count general purpose digital output pin (gpo) separate line_out and hp_out pins headphone drivers on line_out and hp_out pins independent headphone/line_out operation
AD1986 rev. 0 | page 2 of 52 table of contents functional block diagram .............................................................. 4 specifications..................................................................................... 5 ac 97 timing parameters .......................................................... 9 absolute maximum ratings.......................................................... 12 environmental conditions........................................................ 12 esd caution................................................................................ 12 pin configuration and function description ........................... 13 ac 97 registers .............................................................................. 15 register details ............................................................................... 17 reset (register 0x00).................................................................. 17 master volume (register 0x02) ................................................ 17 headphone volume (register 0x04)........................................ 18 mono volume (register 0x06).................................................. 18 pc beep (register 0x0a)........................................................... 19 phone volume (register 0x0c) ................................................ 19 microphone volume (register 0x0e) ...................................... 20 line in volume (register 0x10)................................................ 21 cd volume (register 0x12) ...................................................... 21 aux volume (register 0x16) ................................................... 22 front dac volume (register 0x18)......................................... 22 adc select (register 0x1a)...................................................... 23 adc volume (register 0x1c) .................................................. 24 general-purpose (register 0x20)............................................. 25 audio int and paging (register 0x24) ..................................... 25 power-down ctrl/stat (register 0x26).................................... 26 extd audio id (register 0x28)................................................. 27 extd audio stat/ctrl (register 0x2a)...................................... 28 front dac pcm rate (register 0x2c) ................................... 29 surround dac pcm rate (register 0x2e) ............................ 30 c/lfe dac pcm rate (register 0x30) .................................. 30 adc pcm rate (register 0x32) .............................................. 30 c/lfe dac volume (register 0x36)....................................... 31 surround dac volume (register 0x38) ................................. 31 spdif control (register 0x3a)................................................ 32 eq control register (register 0x60) ....................................... 33 eq data register (register 0x62) ............................................ 34 misc control bits 2 (register 0x70)......................................... 34 jack sense (register 0x72)......................................................... 35 serial configuration (register 0x74)....................................... 37 misc control bits 1 (register 0x76)......................................... 39 advanced jack sense (register 0x78) ...................................... 40 misc control bits 3 (register 0x7a)........................................ 41 vendor id registers (register 0x7c to 0x7e) ........................ 42 codec class/revision register (register 0x60).................. 42 pci subsystem vendor id register (register 0x62, page 01) ....................................................................................................... 43 pci subsystem device id register (register 0x64, page 01)43 function select register (register 0x66, page 01)................. 43 information and i/o register (register 0x68, page 01)........ 44 sense register (register 0x6a, page 01) ................................. 46 jack presence detection................................................................. 48 audio jack styles (nc/no) ...................................................... 48 microphone selection/mixing...................................................... 49 outline dimensions ....................................................................... 50 ordering guide .......................................................................... 50 revision history 10/04initial version: revision 0
AD1986 rev. 0 | page 3 of 52 notes reduced support components the AD1986s many improvements reduce external support components for particular applications. ? multiple microphone sourcing: the mic_1/2, line_in and c/lfe pins may all be selected as sources for microphone input (boost amplifier). ? multiple vref_out pins: each microphone-capable pin group (mic_1/2, line_in and c/lfe) has separate, software controllable vref_out pins, reducing the need for external biasing components. ? internal microphone mixing: any combination of the mic_1/2, line_in and c/lfe pins may be summed to produce the microphone input. this removes the need for external mixing components in those applications that externally mixed microphone sources. ? advanced jack presence detection: using two codec pins, eight resistors and isolated switch jacks, the AD1986 can detect jack insertion on eight separate jacks. previous codecs would have required 8 codec pins and 16 resistors. ? internal microphone/line in/c/lfe sharing: on systems that share the microphone with the c/lfe jack there are no external components required. the micro-phone selector can select the line_in pins in those cases where the microphone and line input devices are swapped. ? internal line in/microphone/surround sharing: on systems that share the line in with the surround jack there are no external components required. ? dual headphone amplifiers: the AD1986 can drive headphones out of the hp_out or line_out pins.
AD1986 rev. 0 | page 4 of 5 2 functional block diagram 04785-0-003 dac slot logic adc slot logic ac '97 i n te rface v 2 . 3 e q coe f s t orage ac '97 control registers gpio eapd analog m i x i ng control jack s e n s e pll reset sync bitclk sdata_out sdata_in jack_sense_a jack_sense_b eapd gpo vref_out (mic1/2) vref_out (c/lfe) vref_out (line_in) vref_filt 20-bit 20-bit - ? adc codec core 24-bit - ? dac 24-bit - ? dac 24-bit - ? dac 24-bit - ? dac eq 24-bit - ? dac eq 24-bit - ? dac - ? adc m g = gain a = attenuation m = mute z = hi-z m g m z g m ga m ga m ga m ga m ga m ga m a m ga m ga m ga mm m ga m ga m ga m ga m ga m ga m m m phone_in cd_l cd_gnd cd_r aux_l aux_r line_in_l cd diff amp line in select microphone selector/ mixing and gain block line_in_r pcbeep_in spr d mz a lfe_out spr d mz a center_out sosel mz a s urr_out_l sosel mz a s urr_out_r line_out_l m a mono_out line_out_r m a hp_out_l m a hp_out_r hp hp mix h psel h psel m a m a hp hp losel losel g z g z g voltage reference AD1986 ac97ck spdif_out spdif tx re cord selec tor pc beep generator mic_1 mic_2 fi g u r e 1 .
AD1986 rev. 0 | page 5 of 52 specifications test conditions, unless otherwise noted. table 1. parameter typ unit temperature 25 c digital supply (dv dd ) 3.3 10% v analog supply (av dd ) 5.0 10% v sample rate (f s ) 48 khz input signal 1,008 hz analog output pass band 20 hzC20 khz v ih 2.0 v v il 0.8 v v ih 2.4 v v il 0.6 v dac test conditions calibrated output ?3 db relative to full scale 10 k? output load: line (surround), mono, center, and lfe 32 ? output load: headphone adc test conditions calibrated 0 db pga gain input ?3.0 db relative to full scale table 2. analog input input voltage min typ max unit mic_1/2, line_in, cd, aux, phone_in (no preamp) 1 vrms 1 c/lfe and surround (when used as inputs) 2.83 v p-p mic_1/2, line_in, c/lfe with 30 db preamp 0.032 vrms 0.089 v p-p mic_1/2, line_in, c/lfe with 20 db preamp 0.1 vrms 0.283 v p-p mic_1/2, line_in, c/lfe with 10 db preamp 0.316 vrms 0.894 v p-p input impedance 2 20 k? input capacitance 2 5 7.5 pf 1 rms values assume sine wave input. 2 guaranteed by design, not production tested. table 3. master volume parameter min typ max unit step size (line_out, hp out, mono out, surround, center, lfe) ?1.5 db output attenuation range (0 db to C46.5 db) ?6.5 db mute attenuation of 0 db fundamental 2 ?80 db table 4. programmable gain amplifieradc parameter min typ max unit step size 1.5 db pga gain range span (0 db to 22.5 db) 22.5 db
AD1986 rev. 0 | page 6 of 52 table 5. analog mixerinput gain/amplifiers/attenuators parameter min typ max unit signal-to-noise ratio (snr) cd to line_out 90 db line, aux, phone to line_out 1 88 db mic_1 or mic_2 to line_out 1 80 db step size: all mixer inputs (e xcept pc beep) ?1.5 db step size: pc beep ?3.0 db input gain/attenuation range: all mixer in puts (+12 db to ?34. 5 db) ?46.5 db 1 guaranteed by design, not production tested. table 6. digital decimation and interpolation filters 1 parameter min typ max unit pass band 0 0.4 f s hz pass band ripple 0.09 db transition band 0.4 f s 0.6 f s hz stop band 0.6 f s hz stop band rejection ?74 db group delay 16/f s s group delay variation over pass band 0 s table 7. analog-to-digital converters parameter min typ max unit resolution 20 bits total harmonic distortion (thd) ?95 db dynamic range (?60 db input, thd + n referenc ed to full scale, a-weighted) ?85 db line inputs (input l, ground r, read r; input r, ground l, read l) ?80 db line_in to other inputs ?100 ?80 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db adc offset error 5 mv
AD1986 rev. 0 | page 7 of 52 table 8. digital-to-analog converters parameter min typ max unit resolution 24 bits total harmonic distortion (line_out drive) ?92 db total harmonic distortion hp_out ?75 db dynamic range (?60 db input, thd + n refere nced to full scale, a-weighted) 91 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.7 db dac crosstalk 1 (input l, zero r, read r_out; input r, zero l, read l_out) ?80 db 1 guaranteed by design, not production tested. table 9. analog output parameter min typ max unit full-scale output voltage: surround, center/lfe, mono_out 1 vrms 2.83 v p-p output impedance 1 300 ? external load impedance 1 10 k? output capacitance 1 15 pf external load capacitance 1,000 pf full-scale output voltage: hp_out, line_out 1 vrms 2.83 v p-p output impedance 1 1 ? external load impedance 1 32 ? output capacitance 1 15 pf external load capacitance 1 1,000 pf vref_filt, a vdd = 5.0 v 2.050 2.250 2.450 v a vdd = 3.3 v 1.125 v vref_out(mic, c/lfe, lin) (x vref [2:0] = 001) 2.250 v (xvref [2:0] = 100, a vdd = 5.0 v) 3.700 v (xvref [2:0] = 100, a vdd = 3.3 v) 2.250 v (xvref [2:0] = 010) 0.0 v current drive 5 ma mute click (muted output, unmuted midscale dac output) 5 mv table 10. static digital specificationsac 97 parameter min typ max unit high level input voltage (v ih ), digital inputs 0.65 dv dd v low level input voltage (v il ) 0.35 dv dd v high level output voltage (v oh ), i oh = 2 ma 0.90 dv dd v low level output voltage (v ol ), i ol = 2 ma 0.10 dv dd v input leakage current ?10 10 a output leakage current ?10 10 a input/output pin capacitance 7.5 pf
AD1986 rev. 0 | page 8 of 52 table 11. power supply (quiescent state) parameter min typ max unit power supply rangeanalog (av dd ) 10% 4.5 5.5 v power supply rangedigital (dv dd ) 10% 2.97 3.63 v power dissipationanalog (av dd )/digital (dv dd ) 365/171.6 mw analog supply currentanalog (av dd ) 73 ma digital supply currentdigital (dv dd ) 52 ma power supply rejection (100 mv pCp signal @ 1 khz) 40 db table 12. power-down state sac 97 (quiescent state) parameter set bits dv dd typ av dd typ unit adc pr0 53.0 45.7 ma front dac pr1 53.7 47.7 ma center dac pri 62.0 53.2 ma surround dac prj 53.5 47.1 ma lfe dac prk 62.0 52.8 ma adc + all dacs pr1, pr0, pri, prj, prk 27.0 14.5 ma mixer pr2 36.6 53.2 ma adc + mixer pr2, pr0 27.6 45.7 ma all dacs + mixer pr2, pr1, pri, prj, prk 12.6 33.0 ma adc + all dacs + mixer pr2, pr1, pr0, pri, prj, prk 2.4 14.5 ma standby pr5, pr4, pr3, pr2, pr1(ijk), pr0 0.0 0.05 ma headphone standby pr6 55.0 53.2 ma line_out hp standby lohpen = 0 62.0 53.2 ma table 13. clock specificationsac 97 1 parameter min typ max unit input clock frequency (reference clock mode) 14.31818 48.000 mhz recommended clock duty cycle 40 50 60 % 1 refer to ac 97, revision 2.3 specific ations for details of clock detection at startup. AD1986 co dec clock source detection mu st follow ac 97, revision 2.3 guidelines.
AD1986 rev. 0 | page 9 of 5 2 a c 97 timing p a r a me ters g u a r an t e e d o v e r o p era t in g t e m p era t ur e ra n g e . refer t o t h e a c 97 sp e c if i c a t ions (re v isio n 2.3 , re l e as e 1.0) fo r f u r t h e r info r m a ti o n . th e sp e c if ic a t ion can b e do w n lo ade d f r o m h t t p : //d e v e l o p er .i n t e l .com/ i a l . s c a lab l epl a t f o r m s /a ud io . reset bit_clk t rst_low t rst2clk 04785-0-005 f i g u re 2. cold r e s e t ti mi ng (c ode c is sup p ly i n g t h e bit_ clk s i g n a l ) table 14. symbol parameter min typ max unit t rst _ low recommended during active (l ow) reset sign al 1.0 s t rst 2 clk reset inactive (high) to bit_cl k active 162.8 400,000 ns sync bit_clk t sync_high t sync2clk 04785-0-006 f i gure 3. w a rm r e s e t t i m i ng table 15. symbol parameter min typ max unit t sy n c _ h igh sync active (hig h) pulse width 1.3 s t sy n c 2clk sync inactive to bitclk startup delay 162.8 ns t setup2rst t off hi-z reset sdata_out sync bit_clk, eapd, spdif_out, sdata_in, digital i/o 04785-0-007 r e 4 . a t e t e s t m o d e table 16. symbol parameter min typ max unit fi g u t set u p2rst setup to rese t i n active (sync, sdata_out) 15 ns t of f rising edge of r e set to hi-z delay 25 ns
AD1986 rev. 0 | page 10 of 52 t clk_low t clk_high t clk_period t sync_low t sync_period t sync_high bit_clk sync 04785-0-008 f i g u re 5. b i t cl ock and sy nc ti m i ng table 17. parameter min typ max units symbol t sy n c _ h igh bitclk high pul s e width 40.5 41.7 ns t clk _ low bitclk low pulse width 39.7 40.6 ns t clk _ period bitclk period 81.4 ns bit_clk frequency 12.288 mhz b i t _ c l k f r e q u e n c y a c c u r a c y 1.0 ppm bit_clk jitter 1 , 2 750 ps t sy n c _ h igh sync active (hig h) pulse width 1.3 s t sy n c _low sync inactive (low) pulse width 19.5 s t sy n c _ p eriod sync period 20.8 s sync frequency 48.0 khz 1 by d e sign, but no t pro d uctio n te s t e d . r d i re ctl y d e pe nde nt o n input cl o c k jitte r. guarante e d 2 output jitte bit_clk sync sdata_in sdata_out bit_clk not to scale slot 1 slot 2 write to 03 26 data pr4 t s2_pdown 04785-0-009 f i gure 6. link l o w p o w e r m o de t i min g 1 8 . parameter min t a b l e symbol typ max units t s2_pdow n e n d a t a _ in low o f s l o t 2 t o b i t _ c l k , s d 0 1 . 0 s
AD1986 rev. 0 | page 11 of 52 bit_clk sync s d a t a _ i n s data_ou t t riseclk t fallclk t risesync t fallsync t risedin t falldin t risedout t falldout 04785-0-010 f i gure 7 . s i gnal r i se a n d f a ll t i m b l e 1 9 . m b o l min typ i t e s t a s y parameter max u n t r i s e c l k 4 6 bit_clk rise ti me 2 n s t f a l l c l k 2 4 bit_clk fall time 6 n s t risesy n c sync rise time 2 4 6 ns t risesy n c sync fall time 2 4 6 ns t ri sedi n sdata_in rise time 2 4 6 ns t ri sedi n sdata_in fall time 2 4 6 ns t ri sedou t sdata_out rise time 2 4 6 ns t ri sedou t sdata_out fal l time 2 4 6 ns bit_clk sdata_out sdata_in sync t co t setup v ih v il v oh v ol t hold 04785-0-011 f i gure 8. link l o w p o w e r m o de ti mi n g ( d et a il) table 20. symbol parameter min typ max unit t co propagation de l a y 25 ns t set u p setup to falling edge of bit_clk 4 ns t hold hold from falling edge of bi t_c l k 3 ns v ih digital signal hi gh level input voltage 0.65 dv dd v v il digital signal lo w level input voltage 0.35 dv dd v v oh digital signal hi gh level output voltage 0.9 dv dd v v ol digital signal lo w level output voltage 0.1 dv dd v
AD1986 rev. 0 | page 12 of 52 absolute maximum ratings table 21. power supply min max unit digital (dv dd ) ?0.3 +3.6 v analog (av dd ) ?0.3 +6.0 v input current ( e x c ept supply pins) 10.0 ma analog input voltage (signal pins) ?0.3 av dd + 0.3 v digital input voltage ( s ignal pins) ?0.3 dv dd + 0.3 v ambient temperature (operating) commercia l industrial 0 C40 +70 +85 c storage temperature ?65 +150 c s t re ss e s g r e a te r t h an t h o s e l i ste d u n de r a b s o l u te m a x i m u m r a t i n g s ma y c a us e p e r m an en t da ma g e t o t h e de v i ce . this is a st re ss r a t i n g on l y and f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e o r a n y o t h e r condi t i on s ab o v e t h o s e indi ca te d i n t h e o p er a t io n a l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . environme n t a l c o n d i t io ns a m b i en t t e m p era t ur e r a ti n g t amb = t case ? (p d ca ) t ca se = cas e t e m p era t ur e in c p d = po w e r d i s s i pa ti o n i n w ca = t h er mal resis t a n c e (cas e-to-a m b ie n t ) ja = th e r m a l r e s i s t a n ce ( j un ctio n - t o - a m b i e n t ) jc = th e r m a l r e s i s t a n ce ( j un ctio n - t o -c a s e ) table 22. ther mal resistance p a c k a g e ja jc ca l q f p 7 6 . 2 c / w 1 7 c / w 5 9 . 2 c / w esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
AD1986 rev. 0 | page 13 of 52 pin conf iguration and function description 04785-0-001 pin 1 identifier top view (not to scale) AD1986 s/pd if_ou t ea pd av dd line _ o ut_ r av ss line _ o ut_ l av dd he adp hone _ r av ss he adp hone _ l av dd mono_ o ut ph on e_in aux _ l aux _ r j ack_ s e n s e _ a j ack_ s e n s e _ b cd_ l cd_ gnd cd_ r mic_ 1 mic_ 2 line _ i n_ l line _ i n_ r dv dd ac97ck gpo dv ss sdata_out bit_clk dv ss sdata_in dv dd sync reset pcbeep surr_out_r surr_out_l av dd vref_out (c/lfe) lfe_out center_out av ss vref_out (line_in) vref_out (mic_1/2) vref_filt av ss av dd 48 47 46 45 44 39 38 37 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 f i gure 9. pin config ur ation ta ble 23. pi n f u nct i on des c ri pt i o ns m n e m o n i c p i n n u m b e r i n p u t / o u p u t d e s c r i p t i o n ac 97ck 2 i external clock i n (14.31818 mh z). sdata_out 5 i ac link seri al data output. input stream. bit_clk 6 o ac link bit clock. 12.288 mhz s e rial data clock. sdata_in 8 i/o ac link se rial data input. output stream. sync 10 i ac link frame sync . reset 11 i ac link reset. master hardware reset. tab l e 24. digital in p u t/outp u t mnemonic pin number input/ o u t p u t d e s c r i p t i o n s/pdif_out 48 o s/pdif output. eapd 47 o external amplifier power-down output. gpo 3 o general-purpose output pin. a digital signal that can be used to co ntrol ex ternal circuitry. table 25. jack sense m n e m o n i c p i n n u m b e r i n p u t / o u p u t d e s c r i p t i o n jack_sense_a 16 i jackse nse 0C3 i n put jack_sense_b 17 i jack sense 4C7 input
AD1986 rev. 0 | page 14 of 52 table 26. analog input/output mnemonic pin number input/ ouput description pcbeep 12 i analog pc beep input. routed to all output capable pins wh en reset is asserted. phone_in 13 i monaural line level input. aux_l 14 i auxiliary left channel input. aux_r 15 i auxiliary right channel input. cd_l 18 i cd-audio-left channel. cd_gnd 19 i cd-audio-analog-ground-r eference (for differential cd input). cd_r 20 i cd-audio-right channel. mic_1 21 i microphone 1 or line-in-left input (see lisel bits in register 0x76). mic_2 22 i microphone 2 or line-in-right input (see lisel bits in register 0x76). line_in_l 23 i line-in-left channel or microp hone 1 input (see oms bits in register 0x74). line_in_r 24 i line-in-right channel or microphone 2 input (see oms bits in register 0x74). center_out 31 i/o center-channel output or microphone 1 input (see oms bits in register 0x74). lfe_out 32 i/o low-frequency-enhanced output or mi crophone 2 input (see oms bits in register 0x74). headphone_l 39 o headphone-out-left ch annel (see hpsel bits in register 0x76). headphone_r 41 o headphone-out-right ch annel (see hpsel bits in register 0x76). line_out_l 43 o line-out (front)left channel (s ee losel bit in register 0x76) (hp drive-capable). line_out_r 45 o line-out (front)right channel (see losel bit in register 0x76) (hp drive-capable). mono_out 37 o monaural output to telephony su bsystem speakerphone. surr_out_l 35 i/o surround-left channel output or line-in- left input (see lisel and sos el bits in register 0x76). surr_out_r 36 i/o surround-right channel output or line-in-ri ght input (see lisel and sosel bits in register 0x76). table 27. filter/reference mnemonic pin number input/ ouput description vref_filt 27 o voltage reference filter. vref_out (mic) 28 o programmable voltage reference o utput (intended for mic bias on the mic_1/2 channels). vref_out (line_in) 29 o programmable voltage reference output (int ended for mic bias on the line_in channels). vref_out (c/lfe) 33 o programmable voltage reference output (intended for mic bias on the c/lfe channels). table 28. power and ground mnemonic pin number input/ ouput description dv dd 1 digital supply voltage (3.3 v). 9 dv ss 4 digital supply return (ground). 7 av dd 25 analog supply voltage (5.0 v or 3.3 v). av dd supplies should be well filtered because supply 34 noise will degrade audio performance. 38 i 42 46 av ss 26 analog supply return (ground). 30 40 44
AD1986 rev. 0 | page 15 of 52 ac 97 registers table 29. register map reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x00 reset x se4 se3 se2 se1 se0 id9 id 8 id7 id6 id5 id4 id3 id2 id1 id0 0x0290 0x02 master volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8080 0x04 headphones volume lm x x lv4 lv3 lv 2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8080 0x06 mono volume m x x x x x x x x x x v4 v2 v2 v1 v0 0x8000 0x0a pc beep m a/ds x f7 f6 f5 f4 f3 f2 f1 f0 v3 v2 v1 v0 x 0x8000 0x0c phone volume m x x x x x x x x x x v4 v3 v2 v1 v0 0x8008 0x0e microphone volume lm x x lv4 lv3 lv2 lv 1 lv0 rm m20 x rv4 rv3 rv2 rv1 rv0 0x8888 0x10 line in volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 0x12 cd volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 0x16 aux volume lm x x lv4 lv3 lv2 lv1 lv 0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 0x18 front dac volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 0x1a adc select x x x x x ls2 ls1 ls0 x x x x x rs2 rs1 rs0 0x0000 0x1c adc volume lm x x x lv3 lv2 lv1 lv0 rm x x x rv3 rv2 rv1 rv0 0x8080 0x20 general purpose x x x x drss1 drss0 mix ms lpbk x x x x x x x 0x0000 0x24 audio int. and paging i4 i3 i2 i1 i0 x x x x x x x pg3 pg2 pg1 pg0 0xxx00 0x26 power-down ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 0x000x 0x28 extd audio id id1 1 id0 x x rev1 rev0 amap ldac sdac cdac dsa1 dsa0 x spdf dra vra 0x0bc7 0x2a extd audio stat/ctrl x x prk prj pri spcv x ldac sdac cdac spsa1 spsa0 x spdif dra vra 0x0xx0 0x2c front dac pcm rate r15 r14 r13 r12 r11 r10 r09 r08 r07 r06 r05 r04 r03 r02 r01 r00 0xbb80 0x2e surr. dac pcm rate r15 r14 r13 r12 r11 r10 r09 r08 r07 r06 r05 r04 r03 r02 r01 r00 0xbb80 0x30 c/lfe dac pcm rate r15 r14 r13 r12 r11 r10 r09 r08 r07 r06 r05 r04 r03 r02 r01 r00 0xbb80 0x32 adc pcm rate r15 r14 r13 r12 r11 r10 r09 r08 r07 r06 r05 r04 r03 r02 r01 r00 0xbb80 0x36 c/lfe dac volume lfem x x lfe4 lfe3 lfe2 lfe1 lfe0 cntm x x cnt4 cnt3 cnt2 cnt1 cnt0 0x8888 0x38 surround dac volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 0x3a spdif control v vcfg spsr x l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy / audio pro 0x2000 0x60 eq control eqm x x x x x x x sym chs bca5 bca4 bca3 bca2 bca1 bca0 0x8080 0x62 eq data cfd15 cfd14 cfd13 cfd12 cfd11 cfd10 cfd9 cfd8 cfd7 cfd6 cfd5 cfd4 cfd3 cfd2 cfd1 cfd0 0xxxxx 0x70 misc. control bits 2 x x x mvref2 mvref1 mvref0 x x mmdis x jsmap cvref2 cvref1 cvref0 x x 0x0000 0x72 jack sense js1 sprd js1 dmx js0 dmx js mt2 js mt1 js mt0 js1 eqb js0 eqb x x js1 md js0 md js1 st js0 st js1 int js0 int 0x0000 0x74 serial configuration slot16 regm2 re gm1 regm0 regm3 oms2 oms1 oms0 spovr lbks 1 lbks0 ints cswp spal spdz splnk 0x1001 0x76 misc. control bits 1 dacz ac97nc 2 msplt sodis 3 cldis x dmix1 dmix0 sprd 2cmic sosel s ru lisel1 lisel0 mbg1 mbg0 0x6010 0x78 advanced jack sense js7st js7int js6st js6int js5st js5int js4st js4int js4-7h x js3md js2md js3st js2st js3int js 2int 0xxxxx 0x7a misc. control bits 3 jsinvb hpsel1 hpsel0 losel jsinva lvre f2 lvref1 lvref0 x x x lohpen gpo mmix x x 0x0000 0x7c vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 0x4144 0x7e vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 0x5378 0x601 codec class/rev x x x cl4 cl3 cl2 cl1 cl 0 rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 0x0002 0x621 pci svid pvi15 pvi14 pvi13 pvi12 pvi11 pvi10 pvi9 pvi8 pvi7 pvi6 pvi5 pvi4 pvi3 pvi2 pvi1 pvi0 0xffff 0x641 pci sid pi15 pi14 pi13 pi12 pi11 pi10 pi9 pi8 pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 0xffff
AD1986 rev. 0 | page 16 of 52 reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x661 function select x x x x x x x x x x x fc3 fc2 fc1 fc0 t/r 0x0000 0x681 function information g4 g3 g2 g1 g0 inv dl4 dl3 dl2 dl1 dl0 iv x x x fip 0xxxxx 0x6a1 sense register st2 st1 st0 s4 s3 s2 s1 s0 or1 or0 sr5 sr4 sr3 sr2 sr1 sr0 0xxxxx 1 codec is always master, id bits are read-only 0 (zeros). 2 bits for the ad198x are backwa rds-compatible only, ac97nc and msplt are read-only 1 (ones). 3 sodis/sosel were lodis/losel in the ad1985. most ad1985 configurati ons swapped line_out and surround pins; these bits really o perated as so not lo.
preliminary technical data AD1986 rev. 0 | page 17 of 52 register details reset (register 0x00) writing any value to this register performs a register reset, which causes all registers to revert to their default values. the serial configuration (0x74) register will not reset the slot16, regm [2:0], spovr, spal, spdz, and splnk. these bits are reset on a ha rd, hardware, or power-on reset. the regm and serial configuration bits are only reset only by an external hardware reset. the ac 97, revision 2.3, page 1 registers codec class/rev (0 x601), pci svid (0x621), pci sid (0x641), function information (0x 681 per supported function), and sense register st [3:0] bits (0x6a1 d [15:13]per supported function) are only reset on a power-on reset. to satisfy the ac 97, revision 2.3 requirements, these registers/bits are sticky across all software and hardware resets. reading this register returns the id code of the part and a code for the type of 3d stereo enhancement. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x00 reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0x0290 table 30. register function the id decodes the capabilities of the AD1986 based on the functions. bit function AD1986 id [9:0] id0 dedicated mic pcm in channel 0 id1 reserved (per ac 97, revision 2.3) 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out support 1 0x290 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 0 id7 20-bit dac resolution 1 id8 18-bit adc resolution 0 id [9:0] (ro) (identify capability) id9 20-bit adc resolution 1 se [4:0] (ro) (stereo enhancement) the AD1986 does not provide hardwa re 3d stereo enhancement (all bits are zero). default: 0x00 x reserved. default: 0 master volume (register 0x02) this register controls the line_out, surround, and center/lfe ou tputs mute and volume controls in unison. each volume sub- register contains five bits, generating 32 volume steps of ?1.5 db each for a range of 0 db to ?46.5db. the headphone output (hp_out) mute and volume are controlled separately by the headphones volume register (0x04).the monaural output (mono_out) mute and volume is controlled separately by the mono volume register (0x06). to control the line_out, surround, and center/lfe volumes separately use the front dac volume register (0x18) for line_out; the surround dac volume register (0x38) for surround; and the c/lfe dac volume register (0x36) for center/lfe. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x02 master volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8080
AD1986 preliminary technical data rev. 0 | page 18 of 52 table 31. register function left/right volume controls th e left/right channel output gains from 0 db to C46.5 db. the least significant bi t represents C1.5 db. l/rm l/rv [4:0] function default 0 0 0000 0 db default 0 0 1111 ?22.5 db attenuation 0 1 1111 ?46.5 db attenuation l/rv [4:0] (left/right volume) 1 x xxxx muted l/rm (left/right mute) mutes the left/right channels inde pendently. default: muted (0x1) x reserved. default: 0 headphone volume (register 0x04) this register controls the hp_out mute and volume controls. each volume subregister contains five bits, generating 32 volume st eps of ?1.5 db each for a range of 0 db to ?46.5 db. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x04 headphones volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8080 table 32. register function left/right volume controls th e left/right channel output gains from 0 db to C46.5 db. the least significant bi t represents C1.5 db. l/rm l/rv [4:0] function default 0 0 0000 0 db default 0 0 1111 ?22.5 db attenuation 0 1 1111 ?46.5 db attenuation l/rv [4:0] (left/right volume) 1 x xxxx muted l/rm (left/right mute) mutes the left/right channels inde pendently. default: muted (0x1) x reserved. default: 0 mono volume (register 0x06) this register controls the mono_out mute and volume control. the volume register contains five bits, generating 32 volume steps of ?1.5 db each for a range of 0 db to ?46.5 db. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x06 mono volume m x x x x x x x x x x v4 v3 v2 v1 v0 0x8000 table 33. register function v [4:0] volume controls the output gain fr om 0 db to C46.5 db. the least si gnificant bit represents -1.5 db. (volume) m v [4:0] function default 0 0 0000 0 db default 0 0 1111 ?22.5 db attenuation 0 1 1111 ?46.5 db attenuation 1 x xxxx muted m (mute) mutes the output. default: muted (0x1) x reserved. default: 0
preliminary technical data AD1986 rev. 0 | page 19 of 52 pc beep (register 0x0a) this controls the level of the analog pc beep or the level and frequency of the digital pc beep. the volume register contains f our bits, generating 16 volume steps of ?3.0 db each for a range of 0 db to ?45.0 db. the tone frequency can be set between 47 hz to 12,0 00 hz or disabled. per intels bios writers guide, the pc beep signal should play via headphone out, line out, and mono out paths. bios algorithm s should unmute the pc beep register and the path to each output, and set the volume levels for playback. when the AD1986 is in reset (the external reset pin is low), the pcbeep_in pin is connected internally to all of the device out put pins (headphone l/r, line_out l/r, mono_out, surround l/r, and center/lfe). there are no amplifiers or attenuators on this path and the external circuitry connected to this pin should anticipate the drive requirements for the multiple output sou rces. headphones connected to output pins will substantially load the signal. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x0a pc beep m a/ds x f7 f6 f5 f4 f3 f2 f1 f0 v3 v2 v1 v0 x 0x8000 table 34. register function controls the gain into the output mixer from 0 db to ?45.0 db. the least significant bit represents ?3.0 db. the gain default is 0 db and muted. m v3...v0 function default 0 0000 0 db default 0 1111 ?45 db attenuation 1 xxxx muted v [3:0] (analog or digital volume) the result of dividing the 48 khz clock by four times this number, allowing tones from 47 hz to 12 khz. a value of 0x00 disables internal pc beep generation. the digitally-generated si gnal is close to a square wave and is not intended to be a high quality signal. f7...f0 function 0000 disabled default 0001 12,000 hz tone f [7:0] (pc beep frequency) 1111 47 hz tone a/ds (pc beep source) selects either the digital pc beep generator (= 0) or analog pcbeep pin (= 1). when the codec is in reset mode the analog pcbeep pin is routed to the outputs via a high impedance path. once ot of reset, this bit must be programmed to a 1 to pass through any signals on the analog pcbeep pin. designers may choose not to conne ct the analog pcbeep pin and use the digital pc beep generator solely. default: digitally-selected (0x0) m (pc beep mute) when this bit is set to 1, the pc beep signal (analog or digital) is muted. default: muted (0x1) x reserved. default: 0 phone volume (register 0x0c) this register controls the phone_in mute and gain to the analog mixer section. the volume register contains five bits, generati ng 32 volume steps of 1.5 db each for a range of 12.0 db to ?34.5 db. this does not control the record adc gain (see register 0x1c ). reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x0c phone volume m x x x x x x x x x x v4 v3 v2 v1 v0 0x8008
AD1986 preliminary technical data rev. 0 | page 20 of 52 table 35. register function controls the gain of this input to the analog mixer from 12.0 db to ? 34.5 db. the least significant bit represents ? 1.5 db. mv [4:0] function default 0 0 0000 12 db gain 0 0 1000 0 db default 0 1 1111 ? 34.5 db attenuation v [4:0] (volume) 1 x xxxx muted m (mute) mutes the input to the an alog mixer. default: muted (0x1) x reserved. default: 0 microphone volume (register 0x0e) this register controls the mic_1 (left) and mic_2 (right) channe ls gain, boost, and mute to the analog mixer section. the volu me register contains five bits, generating 32 volume steps of ?1.5 db each for a range of +12.0 db to ?34.5 db. this does not cont rol the record adc gain (see register 0x1c). in typical stereo microphone applications, the signal paths must be identical and should be set to the same gain, boost, and mu te values. with stereo controls, this input is capable of nonmicrophone sources by disabling the microphone boost (m20 bit = 0). reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x0e microphone volume lm x x lv4 lv3 lv2 lv1 lv0 rm m20 x rv4 rv3 rv2 rv1 rv0 0x8888 table 36. register function controls the left/right channel gains of this input to the analog mixer from +12 db to ? 34.5 db. the least significant bit represents ? 1.5 db. l/rm l/rv [4:0] function default 0 0 0000 12 db gain 0 0 1000 0 db default 0 1 1111 ?34.5 db attenuation l/rv [4:0] (left/right volume) 1 x xxxx mute enables additional gain to increase the microphone sensitivity. this controls the boost of both the mic_1 and mic_2 channels. the nominal gain boost by default is 20 db; however, mbg0 [1:0] bits (register 0x76), allow changing the gain boost to 10 db or 30 db if necessary. m20 mgb0 [1:0] boost gain 0 xx 0 db gain default: disabled 1 00 20 db gain default 1 01 10 db gain m20 (mic_1/2 gain boost) 1 x xxxx mute l/rm (left/right mute) mutes the left/right channels inde pendently. default: muted (0x1) x reserved. default: 0
preliminary technical data AD1986 rev. 0 | page 21 of 52 line in volume (register 0x10) this register controls the line_in gain and mute to the analog mixer section. the volume register contains five bits, generatin g 32 volume steps of ?1.5 db each for a range of +12.0 db to ?34.5 db. this does not control the record adc gain (see register 0x 1c). reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x10 line in volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 table 37. register function controls the left/right channel gains of this input to the analog mixer from 12 db to ? 34.5 db. the least significant bit represents ? 1.5 db. l/rm l/rv [4:0] function default 0 0 0000 12 db gain 0 0 1000 0 db default 0 1 1111 ?34.5 db attenuation l/rv [4:0] (left/right volume) 1 x xxxx muted l/rm (left/right mute) mutes the left/right channels inde pendently. default: muted (0x1) x reserved. default: 0 cd volume (register 0x12) this register controls the cd gain and mute to the analog mixe r section. the volume register contains five bits, generating 32 volume steps of ?1.5 db each for a range of +12.0 db to ?34.5 db. this does not control the record adc gain (see register 0x1c). many operating systems will play cds directly using the digital data from the cd tracks. this control will only affect cd audio playback if it is enabled for analog and this input is connected to the cd player analog connection. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x12 cd volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 table 38. register function controls the left/right channel gains of th is input to the analog mixer from +12 db to C34.5 db. the least significant bit represents C1.5 db. l/rm l/rv [4:0] function default 0 0 0000 12 db gain 0 0 1000 0 db default 0 1 1111 ? 34.5 db attenuation l/rv [4:0] (left/right volume) 1 x xxxx muted l/rm (left/right mute) mutes the left/right channels inde pendently. default: muted (0x1) x reserved. default: 0
AD1986 preliminary technical data rev. 0 | page 22 of 52 aux volume (register 0x16) this register controls the aux_in gain and mute to the analog mixer section. the volume register contains five bits, generating 32 volume steps of ?1.5 db each for a range of +12.0 db to ?34.5 db. this does not control the record adc gain (see register 0x 1c). reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x16 aux volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 table 39. register function controls the left/right channel gains of th is input to the analog mixer from +12 db to ?34.5 db. the least significant bit represents ?1.5 db. l/rm l/rv [4:0] function default 0 0 0000 12 db gain 0 0 1000 0 db default 0 1 1111 ?34.5 db attenuation l/rv [4:0] (left/right volume) 1 x xxxx mute l/rm (left/right mute) mutes the left/right channels inde pendently. default: muted (0x1) x reserved. default: 0 front dac volume (register 0x18) this register controls the front dac gain and mute to the analog mixer section. the volume register contains five bits, generat ing 32 volume steps of ?1.5 db each for a range of +12.0 db to ?34.5 db. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x18 front dac volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 table 40. register function controls the left/right channel gains of this input to the analog mixer from + 12 db to ?34.5 db. the least significant bit represents ?1.5 db. l/rm l/rv [4:0] function default 0 0 0000 +12 db gain 0 0 1000 0 db default 0 1 1111 ?34.5 db attenuation l/rv [4:0] (left/right volume) 1 x xxxx mute l/rm (left/right mute) mutes the left/right channels inde pendently. default: muted (0x1) x reserved. default: 0
preliminary technical data AD1986 rev. 0 | page 23 of 52 adc select (register 0x1a) this register selects the record source for the adc, independently for the right and left channels. the default value is 0x0000 , which corresponds to the mic_1/2 input for both channels. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x1a adc select x x x x x ls2 ls1 ls0 x x x x x rs2 rs1 rs0 0x0000 table 41. register ls [2:0] left record source function 000 mic_1/2 selector left channel default 001 cd_in left 010 muted 011 aux_in left 100 line_in left 101 stereo output mix left 110 mono output mix mono ls [2:0] (left record select) 111 phone_in mono rs [2:0] right record source 000 mic_1/2 selector left channel default 001 cd_in right 010 muted 011 aux_in right 100 line_in right 101 stereo output mix right 110 mono output mix mono rs [2:0] (right record select) 111 phone_in mono table 42. microphone selector oms [2:0] 1 mmix 2 2cmic 3 ms 4 left channel 5 right channel 000 0 0 0 mic_1 (default) 000 0 0 1 mic_2 000 0 1 0 mic_1 mic_2 000 0 1 1 mic_2 mic_1 000 1 x x mic_1 + mic_2 (mixed) 001 0 0 0 line_in left 001 0 0 1 line_in right 001 0 1 0 line_in left line_in right 001 0 1 1 line_in right line_in left 001 1 x x line inleft + right (mixed) 01x 0 0 0 center 01x 0 0 1 lfe 01x 0 1 0 center lfe 01x 0 1 1 lfe center 01x 1 x x center + lfe (mixed) 100 0 0 0 mic_1 + center (mixed) 100 0 0 1 mic_2 + lfe (mixed) 100 0 1 0 mic_1 + center (mixed) mic_2 + lfe (mixed) 100 0 1 1 mic_2 + lfe (mixed) mic_1 + center (mixed) 100 1 x x mic_1 + mic_2 + center + lfe (mixed)
AD1986 preliminary technical data rev. 0 | page 24 of 52 oms [2:0] 1 mmix 2 2cmic 3 ms 4 left channel 5 right channel 101 0 0 0 mic_1 + line_in left (mixed) 101 0 0 1 mic_2 + line_in right (mixed) 101 0 1 0 mic_1 + line_in left (mixed) mic_2 + line_in right (mixed) 101 0 1 1 mic_2 + line_in right (mixed) mic_1 + line_in left (mixed) 101 1 x x mic_1 + mic_2 + line_in left + line right (mixed) 110 0 0 0 line_in left + center (mixed) 110 0 0 1 line_in right + lfe (mixed) 110 0 1 0 line_in left + center (mixed) line_in right + lfe (mixed) 110 0 1 1 line_in right + lfe (mixed) line_in left + center (mixed) 110 1 x x line_in left + line_in right + center + lfe (mixed) 111 0 0 0 mic_1 + line_in left + center (mixed) 111 0 0 1 mic_2 + line_in right + lfe (mixed) 111 0 1 0 mic_1 + line_in left + center (mixed) mic_2 + line_in right + lfe (mixed) 111 0 1 1 mic_2 + line_in right + lfe (mixed) mic_1 + line_in left + center (mixed) 111 1 x x mic_1 + mic_2 + line_in left + line_in right + center + lfe (mixed) 1 to select the alternate pins as a microphone source, see the oms [2:0] bit (register 0x74). 2 to mix the left/right mic channels see mmix bit (register 0x7a). 3 for dual mic recording see 2cmic bit (register 0x76) to enable simultaneous recording into l/r channels. 4 to swap left/right mic channels, see the ms bit (register 0x20) for mic_1/2 selection. 5 the mono_out pin may be connected to the left channel of the microphone selector and is affected by these bits. adc volume (register 0x1c) this register controls the mute and gain of the adc record path. the volume register contains four bits, generating 16 volume s teps of 1.5 db each for a range of 0 db to 22.5 db. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x1c adc volume lm x x x lv3 lv2 lv1 lv0 rm x x x rv3 rv2 rv1 rv0 0x8080 table 43. register function controls the left/right channel gains of this input to the analog mixer from 0 db to 22.5 db the least significant bit represents 1.5 db. l/rm l/rv [3:0] function default 0 0000 0 db default 0 1000 12.0 db gain 0 1111 22.5 db gain l/rv [4:0] (left/right volume) 1 xxxx muted l/rm (left/right mute) mutes the left/right channels inde pendently. default: muted (0x1) x reserved. default: 0
preliminary technical data AD1986 rev. 0 | page 25 of 52 general-purpose (register 0x20) this register should be read before writing to generate a mask for only the bit(s) that need to be changed. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x20 general- purpose x x x x drss1 drss0 mix ms lpbk x x x x x x x 0x0000 table 44. register function default lpbk (loop- back control) this bit enables the digital internal lo op back from the adc to the front dac. this feature is normally used for testing and troubleshooting. see lbks bit in register 0x74 for changing the loop back path to use the surround or center/lfe dacs. default: disabled (0x0) ms (mic select) used in conjunction with the oms [2 :0] (0x74 d10:08]), 2cmic (0x76 d06) and mmix (0x7a d02). selects which mic input goes into the adc0 record selectors mic channel inputs. when set, this bit swaps the left and right channels. selects mono output audio source. mix mono output connection 0 mixconnected to the mono mixer output. default mix (mono output select) 1 micconnected to the left channel of the mic selector and swap. the drss bits specify the slots for th e n+1 sample outputs. pcm l (n+1) an d pcm r (n+1) data are by default provided in output slots 10 and 11. drss [1:0] drss [1:0] function 00 pcm l, r (n+1) data is on slots 10 and 11 default 01 pcm l, r (n+1) data is on slots 7 and 8 drss [1:0] (double rate slot select) 1x reserved x reserved. default: 0 audio int and paging (register 0x24) this register controls the audio interrupt and register paging mechanisms. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x24 audio int and paging i4 i3 i2 i1 i0 x x x x x x x pg3 pg2 pg1 pg0 0xxx00 table 45. register function this register is used to select a descriptor of 16 word pa ges between registers 0x60 to 0x6 f. a value of 0x0 is used to select vendor specific space to maintain compatibility with ac 97 revision 2.2 vendor specific registers. system software can determine implemented pages by writing the pa ge number and reading the value back. if the value read back does not match the value written, the page is not implemented. all imple mented pages must be in consecutive order (i.e. page 0x2 cannot be implemented without page 0x1). pg [3:0] addressing page selection default 000 (page 0) page 0 (vendor) registers default 001 (page 1) page id 01, registers defined in ac 97, revision 2.3 pg [3:0] (page selector (read/write)) page 0xhC0xf reserved software should not unmask the interrupt unless ensu red by the ac 97 controller that no conflict is possible with modem slot 12gpi functionality. ac 97 revision 2.2 co mpliant controllers will not likely support audio codec interrupt infrastructure. in that case, software can poll the in terrupt status after initiating a sense cycle and waiting for sense cycle max delay (defined by software) to determine if an interrupting event has occurred. i0 interrupt mask status 0 interrupt generation is masked default i0 (interrupt enable (read/write)) 1 interrupt generation is unmasked
AD1986 preliminary technical data rev. 0 | page 26 of 52 register function writing a 1 to this bit causes a sense cycle start if supported. if a sense cycle is in progress, writing a 0 to this bit will abort the sense cycle. the data in the sense result register (0x6a, page 01) may or may not be valid, as determined by the iv bit. i1 read write 0 sense cycle completed (o r not initiated) default aborts sense cycle (if in process) 1 sense cycle still in process initiate sense cycle i1 (sense cycle (read/write)) these bits will indicate the ca use(s) of an interrupt. this information should be used to service the correct interrupting event(s). if the interrupt status (bit i4) is set, one or both of these bits must be set to indicate the interrupt cause. hardware will reset these bits back to zero when the inte rrupt status bit is cleared. i2 interrupt status 0 sense status has not changed (di d not cause interrupt). default 1 sense cycle completed or new sense information is available i3 0 gpio status change did not cause interrupt i [3:2] ( interrupt cause (ro)) 1 gpio status change caused interrupt interrupt event is cleared by writing a 1 to this bit. the interrupt bit will chan ge regardless of condition of interrupt enable (i0) status. an interrupt in the gp i in slot 12 in the ac link will follow th is bit change when interrupt enable (i0) is unmasked. if this bit is set, one or both of i3 or i2 must be set to indicate the interrupt cause. i4 read write 0 interrupt clear default no operation i4 (interrupt status (read/write)) 1 interrupt generated clears interrupt x reserved. default: 0 power-down ctrl/stat (register 0x26) the ready bits are read only; writing to ref, anl, dac, and adc has no effect. these bits indicate the status for the AD1986 subsections. if the bit is 1 then that subsection is ready. ready is defined as the subsection able to perform in its nominal state. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x26 power- down ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 0x000x table 46. register adc adc status 0 adc not ready 1 adc sections ready to transmit data adc (ro) (adc section status (ro)) dac front dac status 0 adc not ready adc (ro) ((front dac status (ro)) 1 adc sections ready to transmit data anl analog status 0 analog amplifiers, attenuators and mixers not ready anl (ro) (analog amplifiers, attenuators and mixers status (ro)) 1 analog amplifiers, attenuators and mixers ready
preliminary technical data AD1986 rev. 0 | page 27 of 52 register adc adc status vref_out pin output states controlled by the cv ref , mv ref , and lv ref controls in register 0x70. ref v ref status 0 voltage references, vref and vref_out not ready. ref (ro) (voltage references, v ref and vref_out status (read only)) 1 voltage references, vref, and vref_out up to nominal level. pr0 all adcs and input selectors power down: clearing th is bit enables vref regardless of the state of pr3. default: all adcs and inp ut muxs powered on (0x0). pr1 all dacs power down. also powers down th e eq circuitry. clearing this bit enab les vref regardless of the state of pr3. default: all dacs and eq powered on (0x0). pr2 analog mixer power down. (valid if pr7 = 0). default: analog mixer powered on (0x0). pr3 all v ref and v ref _out pins power down. may be used in combination wi th pr2 or by itself. if all the adcs and dacs are not powered down, setting this bit will have no effect on the v ref and will only power down vref_out. default: all vrefand vref_out pins powered on (0x0). pr4 ac-link interface power down. the reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before pr5 and pr4 are both set. in multiple-codec systems, the master codecs pr4 bit controls the slave codec. in the slave codec th e pr4 bit has no effect except to enable or disable pr5. default: ac-link interface powered on (0x0). pr5 internal clocks disabled. pr5 has no effect unless all adcs, dacs, and the ac-link are powered down (e.g. pr0, pr1, pr4). the reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to co mpletion before pr5 and pr4 are both set. in multiple codec systems, the master codec s pr5 controls the slave codec. pr5 is effective in the slave codec if the master's pr5 bit is clear. default: internal cl ocks enabled (0x0). pr6 powers down the headphone amplifiers. default: hp amp powered on (0x0). eapd eapd pin status 0 sets the eapd pin low, enabling an external power amplifier. default eapd 1 sets the eapd pin high, shutting th e external power amplifier off. x reserved. default: 0 extd audio id (register 0x28) the extended audio id register identifies which extended audio features are supported. a nonzero extended audio id value indica tes one or more of the extended audio features are supported. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x28 extd audio id id1 id0 x x rev1 rev0 amap ldac sdac cdac dsa1 dsa0 x spdf dra vra 0x0bc7 table 47. register description setting function vra (ro) variable rate pcm audio: read only = 1 variable rate pcm audio supported spdif (ro) spdif support: read only = 1 spdif transmitter supported (iec958) dra (ro) double rate audio: read only = 1 double rate audio supported for dac0 l/r dsa [1:0] dac slot assignment (read/write) front dac surround dac c/lfe dac default dsa [1:0] left right left right left right 00 3 4 7 8 6 9 default 01 7 8 6 9 10 11 10 6 9 10 11 3 4 11 10 11 3 4 7 8
AD1986 preliminary technical data rev. 0 | page 28 of 52 register description setting function cdac (ro) pcm center dac: read only = 1 pcm center dac supported sdac (ro) pcm surround dac: read on ly = 1 cm surround dacs supported ldac (ro) pcm lfe dac: read only = 1 pcm lfe dac supported amap (ro) slot dac mappings: read only = 1 codec id based slot/dac mappings rev [1:0] (ro) ac97 version: read only = 10 codec is ac 97, revision 2.3 compliant id [1:0] (ro) codec configuration: read only = 00 primary ac 97 x reserved default: 0 extd audio stat/ctrl (register 0x2a) the extended audio status and control register is a read/write register that provides status and control of the extended audio features. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x2a extd audio stat/ctrl x x prk prj pri spcv x ldac sdac cdac spsa1 spsa0 x spdif dra vra 0x0xx0 table 48. register function enables variable rate audio mode. enables sample rate registers and slotreq signaling. vra vra state default 0 disabled, sample rate 48 khz for all adcs and dacs default vra (variable rate audio) 1 enabled, adcs and dacs can be set to variable sample rates dra = 1. enables double-rate audio mode in which data fr om pcm l and pcm r in output slots 3 and 4 is used in conjunction with pcm l (n + 1) and pcm r (n + 1) data to provide dac streams at twice the sample rate designated by the pcm front sample rate control register. wh en using the double rate audio, only the front dacs are supported and all other dacs (surround, center, and lfe) are automatically powered down . the slot that contains the additional data is determined by the drss[1:0] bits (0x20 d [11:10]). note that dra can be used without vra; in which case the converter rates are forced to 96 khz if dra = 1. dra dra state default 0 disabled, dacs sample at the programmed rate default dra (double rate audio) 1 enabled, dacs sample at tw ice (2) the programmed rate spdif transmitter subsystem enable/disable bit (read/write) this bit is also used to validate that the spdif transmitte r output is actually enabled. the sp dif bit is only allowed to be se t high, if the spdif pin (48) is pulled down at power-up enabling the codec transmitter logic. if the spdif pin is floating or pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a lo w, indicating that the spdif transmitter is not available. this bit must always be read back, to verify that the spdif transmitter is actually enabled. spdif function 0 disables the s/pdif transmitter default 1 enables the s/pdif transmitter spdif ac '97 revision 2.2 amap compliant default spdif slot assignments. spsa [1:0] s/pdif slot assignment 00 3 and 4 default 01 7 and 8 10 6 and 9 spsa [1:0] (spdif slot assignment bits: (read/write)) 11 10 and 11 cdac center dac status 0 center dac not ready 1 center dac section ready to receive data 0 surround dac not ready cdac (ro) (center dac status (ro)) 1 surround dac section ready to receive data
preliminary technical data AD1986 rev. 0 | page 29 of 52 register function ldac lfe dac status 0 lfe dac not ready ldac (ro) (lfe dac status (ro)) 1 lfe dac section ready to receive data indicates the status of the spdif trans mitter subsystem, enabling the driver to determine if the currently programmed spdif configuration is supported. spcv is always valid, independent of the spdif enable bit status. spcv s/pdif configuration status 0 invalid spdif configuration {spsa, spsr, dac slot rate, drs} spcv (ro) (spdif configuration valid (ro)) 1 valid spdif configuration actual status reflected in the cdac (0x3a d06) bit. pri center dac power status 0 power-on center dac default pri (center dac power-down) 1 power-down center dac actual status reflected in the sdac bit. prj surround dacs power control 0 power-on surround dacs default prj (surround dacs power- down) 1 power-down surround dacs actual status reflected in the ldac bit. prk lfe dacs power control 0 power-on lfe dac default prk (lfe dac power-down) 1 power-down lfe dac x reserved. default: 0 front dac pcm rate (register 0x2c) this read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in hz. if the v ra bit (0x2a d00) is 0 this register is forced to 48 khz (0xbb80). if vra is 1, this register may be programmed with the actual sample rate. to use 96 khz in ac 97 mode set the double rate audio (dra) bit (0x2a d01). when using dra in ac 97, only the front dacs are supported and all other dacs (surround, center, and lfe) are automatically powered down. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x2c front dac pcm rate r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 0xbb80 table 49. register function r [15:0] (sample rate) the sampling frequency range is from 7 khz (0x01b58) to 48 khz (0xbb80) in 1 hz increments. if 0 is written to vra, then the sample rates are reset to 48k.
AD1986 preliminary technical data rev. 0 | page 30 of 52 surround dac pcm rate (register 0x2e) this read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in hz. if the vra bit (0x2a d00) is 0, this register is forced to 48 khz (0xbb80). if vra is 1, this register may be programmed with the actual sampl e rate. if the dra bit (0x2a d01) is set, the surround dac is inoperative and automatically powered down. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x2e surr_1 dac pcm rate r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 0xbb80 table 50. register function r [15:0] (sample rate) the sampling frequency range is from 7 khz (0x01b58) to 48 khz (0x bb80) in 1 hz increments. if ze ro is written to vra then the sample rates are reset to 48k. c/lfe dac pcm rate (register 0x30) this read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in hz. if the vra bit (0x2a d00) is 0 this register is forced to 48 khz (0xbb80). if vra is 1, this register may be programmed with the actual sample rate. if the dra bit (0x2a d01) is set, the c/lfe dac is inoperative and automatically powered down. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x30 c/lfe dac pcm rate r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 0xbb80 table 51. register function r [15:0] (sample rate) the sampling frequency range is from 7 khz (0x01b58) to 48 khz (0xbb80) in 1 hz increments. if 0 is written to vra then the sample rates are reset to 48k. adc pcm rate (register 0x32) this read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in hz. if the v ra bit (0x2a d00) is 0 (zero) this register is forced to 48 khz (0xbb80). if vra is 1, this register may be programmed with the actual sampl e rate. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x32 adc 0 pcm rate r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 0xbb80 table 52. register function r [15:0] (sample rate) the sampling frequency range is from 7 khz (0x01b58) to 48 khz (0xbb80) in 1 hz increments. if 0 is written to vra then the sample rates are reset to 48k.
preliminary technical data AD1986 rev. 0 | page 31 of 52 c/lfe dac volume (register 0x36) this register controls the center/lfe dac gain and mute to the output selector section. the volume register contains five bits, generating 32 volume steps of ?1.5 db each for a range of +12.0 db to ?34.5 db. note that the left/right association of the center and lfe channels can be swapped at the codec outputs by setting the cswp bit in register 74h. these controls remain unchanged regardless of the state of cswp. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x36 c/lfe dac volume lfem x x lfe4 lfe3 lfe2 lfe1 lfe 0 cntm x x cnt4 cnt3 cnt2 cnt1 cnt0 0x8888 table 53. register function controls the gain of the center channel to the output selector section from +12. 0 db to ?34.5 db. the least significant bit represents ?1.5 db. cntm cnt [4:0] function default 0 0 0000 +12 db gain 0 0 1000 0 db attenuation default 0 1 1111 ?34.5 db attenuation cnt [4:0] (center volume) 1 x xxxx muted cntm (center mute) mutes the center channel. default: muted (0x1) controls the gain of the lfe channel to the output selector section from +12.0 db to ?34.5 db. the least significant bit represents ?1.5 db. lfem lfe[4:0] function 0 0 0000 +12 db gain 0 0 1000 0 db attenuation default 0 1 1111 ?34.5 db attenuation lfe [4:0] (lfe volume) 1 x xxxx muted lfem (lfe mute) mutes the lfe channel. default: muted (0x1) x reserved. default: 0 surround dac volume (register 0x38) this register controls the surround dac gain and mute to the output selector section. the volume register contains five bits, generating 32 volume steps of ?1.5 db each for a range of +12.0 db to ?34.5 db. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x18 surround dac volume lm x x lv4 lv3 lv2 lv1 lv0 rm x x rv4 rv3 rv2 rv1 rv0 0x8888 table 54. register function controls the left/right channel gains of this input to the output selector section from +12 db to -34.5 db. the least significant bit represents ?1.5 db. l/rm l/rv [4:0] function default 0 0 0000 +12 db gain 0 0 1000 0 db default 0 1 1111 ?34.5 db attenuation l/rv [4:0] (left/right volume) 1 x xxxx muted l/rm (left/right mute) mutes the left/right channels inde pendently. default: muted (0x1) x reserved. default: 0
AD1986 preliminary technical data rev. 0 | page 32 of 52 spdif control (register 0x3a) register 0x3a is a read/write register that controls spdif func tionality and manages bit fields propagated as channel status (o r subframe in the v-case). with the exception of v, this register should only be written to when the spdif transmitter is disabled (spdif bit in register 0x2a is 0). this ensures that control and status information start up correctly at the beginning of spdif transmission . reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x3a spdif control v vcfg spsr x l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy /audio pro 20000x table 55. register function indicates professional use of the audio stream. pro state default 0 consumer use of channel default pro (professional) 1 professional use of channel indicates that the data is pcm or another format (such as ac3). /audio state 0 data in pcm format default /audio (nonaudio) 1 data in non-pcm format allows receivers to make co pies of the digital data. copy state 0 copyright asserted default copy (copyright) 1 copyright not asserted disables filter pre-emphasis. pre state 0 filter pre-emphasis is 50/15 sec default pre (pre-emphasis) 1 no pre-emphasis cc [6:0] (category code) programmed according to iec standards, or as appropriate. l (generation level) programmed according to iec standards, or as appropriate. chooses between 48.0 khz and 44.1 khz s/pdif transmitter rate. spsr transmit sample rate 0 44.1 khz 1 48.0 khz default spsr (spdif transmit sample rate) when asserted, this bit forces the spdif stream validity flag (bit < 28 > within each spdif l/r subframe) to be controlled by the validity bit (d15) in register 0x3a (spdif control register). vcfg v validity bit state reset default: 0 0 0 managed by codec error detection logic default 0 1 forced high, indicating subframe data is invalid 1 0 forced low, indicating subframe data is valid vcfg (validity force bit) 1 1 forced high, indicating subframe data is invalid v (validity) this bit affects the validity flag, (bit <28 > transmitted in each spdif l/r subframe) and enables the spdif transmitter to maintain connection during error or mute conditions. note that the vcfg bit (0x3a d14) will force the validity flag high (valid ) or low (invalid). see the vcfg bit description. v state 0 each spdif subframe (l+r) has bit <28> set to 1 default this tags both samples as invalid 1 each spdif subframe (l+r) has bit <28> set to 0 for valid data and 1 for invalid data (error condition) x reserved. default: 0
preliminary technical data AD1986 rev. 0 | page 33 of 52 eq control register (register 0x60) register 0x60 is a read/write register that controls equalizer function and data setup. the register also contains the biquad a nd coefficient address pointer, which is used in conjunction with the eq data register (0x78) to setup the equalizer coefficients. the reset d efault disables the equalizer function until the coefficients can be properly set up by the software and sets the symmetry bit to allo w equal coefficients for left and right channels. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x60 eq control eqm x x x x x x x sym chs bca5 bca4 bca3 bca2 bca1 bca0 0x8080 table 56. biquad and coefficient address pointer bca [5,0] biquad 0 coef a0 bca [5,0] = 011011 biquad 0 coef a1 bca [5,0] = 011010 biquad 0 coef a2 bca [5,0] = 011001 biquad 0 coef b1 bca [5,0] = 011101 biquad 0 coef b2 bca [5,0] = 011100 biquad 1 coef a0 bca [5,0] = 100000 biquad 1 coef a1 bca [5,0] = 011111 biquad 1 coef a2 bca [5,0] = 011110 biquad 1 coef b1 bca [5,0] = 100010 biquad 1 coef b2 bca [5,0] = 100001 biquad 2 coef a0 bca [5,0] = 100101 biquad 2 coef a1 bca [5,0] = 100100 biquad 2 coef a2 bca [5,0] = 100011 biquad 2 coef b1 bca [5,0] = 100111 biquad 2 coef b2 bca [5,0] = 100110 biquad 3 coef a0 bca [5,0] = 101010 biquad 3 coef a1 bca [5,0] = 101001 biquad 3 coef a2 bca [5,0] = 101000 biquad 3 coef b1 bca [5,0] = 101100 biquad 3 coef b2 bca [5,0] = 101011 biquad 4 coef a0 bca [5,0] = 101111 biquad 4 coef a1 bca [5,0] = 101110 biquad 4 coef a2 bca [5,0] = 101101 biquad 4 coef b1 bca [5,0] = 110001 biquad 4 coef b2 bca [5,0] = 110000 biquad 5 coef a0 bca [5,0] = 110100 biquad 5 coef a1 bca [5,0] = 110011 biquad 5 coef a2 bca [5,0] = 110010 biquad 5 coef b1 bca [5,0] = 110110 biquad 5 coef b2 bca [5,0] = 110101 biquad 6 coef a0 bca [5,0] = 111001 biquad 6 coef a1 bca [5,0] = 111000 biquad 6 coef a2 bca [5,0] = 110111 biquad 6 coef b1 bca [5,0] = 111011 biquad 6 coef b2 bca [5,0] = 111010 table 57. register function swaps the blocks that are used for symmetry coe fficients. only valid when the sym bit is set. chs function default 0 selects left channel coeffi cients data block default chs (channel select) 1 selects right channel coefficients data block when set to 1 this bit indicates that the le ft and right channel coefficients are equal. this shortens the coefficients setup sequence since only the left channel coefficients need to be addressed and setup. the right channel coefficients are simultaneously copied into memory. sym function 0 left and right channels can use different coefficients sym (symmetry) 1 indicates that the left and right ch annel coefficients are equal default when set to 1, this bit disables the eq ualizer function (allows all data pass-throug h). the reset default sets this bit to 1 disabling the equalizer function until the biquad coefficients can be properly set. eqm function 0 eq is enabled. eqm (equalizer mute) 1 eq is disabled. data will pass-thru without change. default x reserved. default: 0
AD1986 preliminary technical data rev. 0 | page 34 of 52 eq data register (register 0x62) this read/write register is used to transfer eq biquad coefficients into memory. the register data is transferred to, or retrie ved from the address pointed by the bca bits in the eq cntrl register (0x60). data will only be written to memory, if the eqm bit (register 0x60 bit 15) is asserted. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x62 eq data cfd15 cfd14 cfd13 cfd12 cfd11 cfd10 cfd9 cfd8 cfd7 cfd6 cfd5 cfd4 cfd3 cfd2 cfd1 cfd0 0xxxxx table 58. register function cfd [15:0] (coefficient data) the biquad coefficients are fixed point format values with 16 bi ts of resolution. the cfd15 bit is the msb and the cfd0 bit is the lsb. misc control bits 2 (register 0x70) reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x70 misc control bits 2 x x x mvref 2 mvref 1 mvref 0 x x mmdis x jsmap cvref 2 cvref 1 cvref 0 x x 0x0000 table 59. register function cvref [2:0] (c/lfe vref_out control) sets the voltage/state of the c/lfe vref_out signal. vref_out is used to power microphone style devices plugged into the connected jack circ uitry. the vref_out pin must be co nnected to both the left and right channels through external resistors to function properly. selections other than those defined are invalid and should not be programmed. c/lfe vref_out setting cvref [2:0] 5.0 av dd 3.3 v av dd default 000 hi-z hi-z default 001 2.25 v 2.25 v 010 0v 0v 100 3.70 v 2.25 v jsmap (jack sense mapping) the AD1986 supports two different methods of mapping the jack_sense_a/b resistor tree to bits js [7:0]. use these bits to change fr om the default mapping to the alternate method. jsmap function 0 default jack sens e mapping default 1 alternate jack sense mapping mmdis (mono mute disable) disables the automatic muting of the mono_out pin by jack sense events (see advanced jack sense bits js [3:0] (0x76 d [05:04], 0x72 d [05:04]). mmdis function 0 automute can occur default 1 automute disabled mvref [2:0] (mic vref_out) sets the voltage/state of the microphone vref_out signal . vref_out is used to power microphone style devices plugged into the connected jack circ uitry. the vref_out pin must be co nnected to both the left and right channels through external resistors to function properly. selections other than those defined are invalid and should not be programmed. mic_1/2 vref_out setting mv ref [2:0] 5.0 av dd 3.3 v av dd 000 hi-z hi-z default 001 2.25 v 2.25 v 010 0 v 0 v 100 3.70 v 2.25 v x reserved. default: 0
preliminary technical data AD1986 rev. 0 | page 35 of 52 jack sense (register 0x72) all register bits are read/write except for js0st and js1st, which are read only. important: please refer to table 72 to understand how jack_sense_a and jack_sense_b codec pins translate to js1and js0. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x72 jack sense js1 sprd js1 dmx js0 dmx jsmt 2 jsmt 1 jsmt 0 js1 eqb js0 eqb x x js1 md js0 md js1 st js0 st js1 int js0 int 0x0000 table 60. register function indicates js0 has generated an interrupt. remains set until the so ftware services js0 interrupt; i.e., js0 isr should clear thi s bit by writing a 0 to it. 1. interrupts are generated by valid state changes of js pins. 2. interrupt to the system is actually an or combination of this bit and js3 js0 int. 3. the interrupt implementation path is se lected by the ints bit (register 0x74). 4. it is also possible to generate a software system interrupt by writing a 1 to this bit. js0int read write 0 js0 did not generate interrupt no operation js0int (js0 interrupt status) 1 js0 generated interrupt clears js0int bit indicates js1 has generated an interrupt. remains set until the so ftware services js1 interrupt; i.e., js1 isr should clear thi s bit by writing a 0 to it. see js0int de scription above for additional details. js1int read write 0 js1 did not generate interrupt no operation js1int (js1 interrupt status) 1 js1 generated interrupt clears js1int this bit always reports the logic state of js0. on mic jack sensing: depending on the applications circuit, the logic state for jack sense pins can be the opposite of that on other jacks. software needs to be aware of this is interpreting the js event as a plug in our out event. js0st function default 0 js0 is low (0) js0st (ro) (js0 state (ro)) 1 js0 is high (1) this bit always reports the logic state of js1. mic jack sensin g: depending on the applications circuit, the logic state for js pins can be the opposite to the other jacks. js1st function 0 js1 is low (0) js1st (ro) (js1 state (read only)) 1 js is high (1) this bit selects the operation mode for js0. js0md function 0 jack sense modejs0int must be polled by software default js0md (js0 mode) 1 interrupt modecodec will genera te an interrupt on js0 event this bit selects the operation mode for js1. js1md function 0 jack sense modejs1int must be polled by software default js1md (js1 mode) 1 interrupt modecodec will genera te an interrupt on js1 event this bit enables js0 to control the eq by pass. when this bit is set to 1, js0 = 1 will cause the eq to be bypassed. js0eqb function 0 js0 does not a ffect eq default js0eqb (js0 eq bypass enable) 1 js0 = 1 will cause the eq to be bypassed this bit enables js1 to control the eq bypass. when this bit is set to 1, j s1=1 will cause the eq to be bypassed. js1eqb function 0 js1 does not a ffect eq default js1eqb (js1 eq bypass enable) 1 js1 = 1 will cause the eq to be bypassed
AD1986 preliminary technical data rev. 0 | page 36 of 52 register function jsmt [2,0] (js mute enable selector) these 3 bits select and enable the ja ck sense muting action. see table 61. js0dmx (js0 down- mix control enable) this bit enables js0 to control the down- mix function. this function allows a digital mix of 6-channel audio into 2-channel audio. the mix can then be routed to the ster eo line_out or hp_out jacks. when this bit is set to 1, js0 = 1 will activate the down-mix conversion. see dmix description in register 0x76. the dmix bits select the down-mix implementation type and can also force the function to be activated. js0dmx function 0 js0 does not affect down mix default 1 js0 = 1 activates the 6- to 2-channel down mix this bit enables js1 to control the down-mix function (see the js0dmx description abo ve). when this bit is set to 1, js1 = 1 will activate the down-mix conversion. js1dmx function 0 js1 does not affect down-mix default js1dmx (js1 down- mix control enable) 1 js1 = 1 activates the 6- to 2-channel down-mix this bit enables the 2-channel to 6-channel audio spread function when jss are active (logic state 1). note that the sprd bit can also force the spread function without being gated by the jack senses. please see this bits description in register 0x76 for a better understanding of the spread function. jssprd function 0 js1 does not affe ct spread default jssprd (js spread control enable) 1 j10 = 1 activates spread x reserved. default: 0 table 61. jack sense mute selections (jsmt) ref js1 js0 jsmt2 jsmt1 jsmt0 hp out line out c/lfe out surr out mono out notes 0 out (0) out (0) 0 0 0 active active ac tive active active js0 and js1 ignored 1 out (0) in (1) 0 0 0 active active active active active 2 in (1) out (0) 0 0 0 active active active active active 3 in (1) in (1) 0 0 0 active active active active active 4 out (0) out (0) 0 0 1 active fmute fm ute fmute active js0 no mute action 5 out (0) in (1) 0 0 1 active fmute fmute fmute active js1 mutes mono and enables line_out + surr_out + c/lfe 6 in (1) out (0) 0 0 1 active active active active fmute 7 in (1) in (1) 0 0 1 active active acti ve active fmute standard 6 chan config 8 out (0) out (0) 0 1 0 fmute active fmute fmute active js0 no mute action, swapped hp_out and line_out 9 out (0) in (1) 0 1 0 fmute active fmute fmute active js1 mutes mono and enables hp_out + surr_out + c/lfe 10 in (1) out (0) 0 1 0 active active active active fmute 11 in (1) in (1) 0 1 0 active active active active fmute standard 6 chan config no swap 12 out (0) out (0) 0 1 1 ** ** ** ** ** **reserved 13 out (0) in (1) 0 1 1 ** ** ** ** ** 14 in (1) out (0) 0 1 1 ** ** ** ** ** 15 in (1) in (1) 0 1 1 ** ** ** ** ** 16 out (0) out (0) 1 0 0 active fmute fmute fmute active js0 = 0 and js1 = 0 enables mono 17 out (0) in (1) 1 0 0 active active active active fmute js1 = 1 enabled front only 18 in (1) out (0) 1 0 0 active fmute fmute fmute fmute js0 = 1 and js1 = 0 enables all rear 19 in (1) in (1) 1 0 0 active fmute fmut e fmute fmute 6 chan config with front jack wrap back
preliminary technical data AD1986 rev. 0 | page 37 of 52 ref js1 js0 jsmt2 jsmt1 jsmt0 hp out line out c/lfe out surr out mono out notes 20 out (0) out (0) 1 0 1 fmute fmute fmut e fmute active js0 no mute action 21 out (0) in (1) 1 0 1 fmute fmute fmute fmute active js1 mutes mono and enables all rear. 22 in (1) out (0) 1 0 1 active active active active fmute 23 in (1) in (1) 1 0 1 active active active active fmute standard 6 chan config swapped hp_out and line_out 24 out (0) out (0) 1 1 0 ** ** ** ** ** **reserved 25 out (0) in (1) 1 1 0 ** ** ** ** ** 26 in (1) out (0) 1 1 0 ** ** ** ** ** 27 in (1) in (1) 1 1 0 ** ** ** ** ** 28 out (0) out (0) 1 1 1 ** ** ** ** ** **reserved 29 out (0) in (1) 1 1 1 ** ** ** ** ** 30 in (1) out (0) 1 1 1 ** ** ** ** ** 31 in (1) in (1) 1 1 1 ** ** ** ** ** fmute = output is forced to mute independent of the respective volume register setting. active = output is not muted and its status is dependent on the respective volume register setting. out = nothing is plugged into the jack and therefore the js status is 0 (via the load resistor pull-down action). in = jack has plug inserted and therefore the js status is 1 (via the codec js pin internal pull-up). serial configuration (register 0x74) when register 0x00 is written (soft reset) the slot 16, regm [2:0], spovr, spal, spdz, and splnk bits do not reset. all bits ar e reset on a hardware reset or power-on reset. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x74 serial configuration slot 16 regm2 regm1 regm0 regm3 oms2 oms1 om0 spovr lbks1 lbks0 ints cswp spal spdz sp lnk 0x1001 table 62. register function default this bit enables the s/pdif to link with the front dacs for data requesting. when li nked the s/pdif and front dacs should be set to the same data rate as th ey both generate data requests at the front dacs request rate. splnk function 0 s/pdif and front dacs are not linked splnk (s/pdif link) 1 s/pdif and front dacs are linked default sets data fill mode for s/pdif transmitter fifo under-runs. when this bit is set to on (1) the s/pdif and adc rates should be set to the same rate. spdz on under-runs 0 repeat last sample out the s/pdif stream default spdz (s/pdif dacz) 1 forces midscale sample out the s/pdif stream spal s/pdif transmitter source 0 connected to the ac-link stream default spal (s/pdif adc loop around) 1 connected to the digital adc stream swaps the center/lfe channels. some systems have a swappe d external connection for th e center and lfe channels. setting this bit will swap these channels in ternal to the codec. note that the center and lfe controls do not change and remain at the same addresses and bit assignments. cswp center pin lfe pin 0 center channel lfe channel default (cswp center/lfe swap) 1 lfe channel center channel this bit selects the audio interrupt implementation path. note that this bit does not generate an interrupt, rather it steers t he path of the generated interrupt. ints interrupt mode ints (interrupt mode select) 0 bit 0 slot 12 (modem interrupt) default
AD1986 preliminary technical data rev. 0 | page 38 of 52 register function default 1 slot 6 valid bit (mic adc interrupt) these bits select the internal digital loop-back path when lpbk bit is active (see register 0x20). lbks [1:0] interrupt mode 00 loop back through the front dacs default 01 loop back through the surround dacs 10 loop back through the center and lfe dacs (center dac loops back from the adc left channel, the lfe dac from the adc right channel) lbks [1:0] loop-back selection 11 reserved use this bit to enable s/pdif operation even if the ex ternal s/pdif detection resistor is not installed. spovr s/pdif detection 0 external resistor determines the presence of s/pdif default spovr (s/pdif enable override) 1 enable s/pdif operation selects the source of the microphone gain noost amplifiers. th ese bits work in conjuction with the 2cmic (0x76 d06), ms (0x20 d08), and mmix (0x7a d08) bits. oms [2:0] left channel 000 mic pins default 001 line_in pins 01x c/lfe pins 100 mix of mic and c/lfe pins 101 mix of mic and line_in pins 110 mix of line_in and c/lfe pins oms [2:0] optional microphone selector 111 mix of mic, line_in and c/lfe pins regm [3:0] bit mask indicating which codec is be ing accessed in a chained codec configuration. regm0master codec register mask default regm1slave 1 codec register mask regm2slave 2 codec register mask regm3slave 3 codec register mask slot 16 enable 16-bit slot mode: slot16 makes all ac link slots 16 bits in length, formatted into 16 slots . this is a preferred mode fo r dsp serial port interfacing. slot 16 function 0 standard ac 97 operation default 1 all ac link s slots are 16 bits x reserved default: 0
preliminary technical data AD1986 rev. 0 | page 39 of 52 misc control bits 1 (register 0x76) reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 76h misc control bits 1 dacz ac97nc msplt sodis cldis x dmix 1 dmix0 sprd 2cmic sosel sru lisel1 lisel0 mbg1 mbg0 6010 table 63. register function these two bits allow changing both mic preamp gain bl ocks from the nominal 20 db gain boost. both mic_1/2 and mic_2 preamps will be set to the same selected gain. this gain setting only takes affect while bit d6 (m20) on the mic volume register (0x0e) is set to 1, otherwise the mic boost blocks have a gain of 0 db. mgb [1:0] microphone boost gain default 00 20 db default 01 10 db 10 30 db mbg [1:0] (mic boost gain select register) 11 reserved selects the source of the internal line_in signals. lisel [1:0] line_in selection 00 line_in pins default 01 surround pinsplaces surround outputs in hi-z state lisel [1:0] (line_in selector) 1x mic_1/2 pins controls all dac sample rate locking. sru surround state 0 all dac sample rates are locked to the front sample rate sru (sample rate unlock) 1 front, surround and lfe sample rate s can be set independently default selects either the surround dac or analog mixer as the source driving the surro und output pin amplifier. sosel surround source 0 surround dacs default sosel (surround amplifier input selection) 1 analog mixer 2cmic (2-channel mic select) used in conjunction with the oms [2 :0] (0x74 d10:08]), ms (0x20 d08), and mmix (0x7a d02) bits to set the microphone selection. this bit enables simultaneous re cording from mic_1 and mic_2 inputs, using a stereo microphone array. if the mmix (0x7a d02) bit is set this bit is ignored. 2cmic 2 channel mic state 0 both outputs are driven by the le ft channel of the selector default 1 stereo operation, the left and right channels are driven separately sprd (spread enable) this bit enables spreading of 2-channel media to all 6- output channels. this functi on is implemented in the analog section by using the output selector controls lines for the center/lfe, su rround and line_out output channels. the jack sense pins can also be setup to contro l (gate) this function depending on the jssprd bit (see register 0x72). the sprd bit operates independently and does not affect the losel and hpsel operation. sprd spread state 0 no spreading occurs unless ac tivated by jack sense default 1 the spdr selector drives the center and lfe outputs from the mono_out cldis (c/lfe output enable) controls the hi-z state of the surround_l/r output pins. pi ns are placed into a hi-z mode by software control or when they are selected as inputs to the mic_ 1/2 selector (see the oms [2:0] bits 740x d [10:08]). cldis c/lfe output state 0 outputs enabled default 1 outputs tristated
AD1986 preliminary technical data rev. 0 | page 40 of 52 register function dmix [1:0] (down mix mode select) provides analog down-mixing of the center, lfe and/or surround channels into the mixer channels. this allows the full content of 5.1 or quad media to be played thro ugh stereo headphones or speakers. the jack sense pins can also be setup to control (gate) this function depending on the js0dmx and js1dmx bits (0x72 d [14:13]). dmix [1:0] down-mix state 0x no down-mix unless acti vated by jack sense default 10 selects 6-to-4 down-mix. the center and lfe channels are summed equally into the mixer l/r channels 11 selects 6-to-2 down-mix. in a ddition to the center and lfe channels, the surround channels are summed into the mixer l/r channels controls the hi-z state of the surround output pins. pins are placed into a hi-z mode by software control or when they are selected as inputs to the line_in selector (see the lisel [1:0] bits 0x76 d [03:02]). cldis surround_out state 0 outputs enabled default sodis (surround output enable) 1 outputs tri-stated (hi-z) msplt (ro) (mute split) separates the left and right mutes on all volume register s. this bit is read-only 1 (one) on the AD1986 indicating that mute split is always enabled. ac 97nc (ro) (ac 97 no compatibility mode) changes addressing to adi model (vs. true ac 97 de finition). this bit is re ad-only 1 (one) on the AD1986 indicating that adi addre ssing is always enabled. determines dac data fill under starved condition. dacz dac fill state 0 dac data is repeated when dacs are starved for data default dacz (dac zero-fill) 1 dac data is zero-filled when dacs are starved for data x reserved. default: 0 advanced jack sense (register 0x78) all register bits are read/write except for jsxst bits, which are read-only. important: please refer to table 72 to understand how jack_sense_a and jack_sense_b codec pins translate to js7js2. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x78 advanced jack sense js7 st js7 int js6 st js6 int js5 st js5 int js4 st js4 int js4- 7h x js3 md js2 md js3 st js2 st js3 int js2 int 0xxxxx table 64. register function js [7:2] int indicates jsx has generated an interrupt. remains set until the software services jsx interrupt ; i.e., jsx isr should clear this bit by writing a 0 to it. 1. interrupts are generated by valid state changes of jsx. 2. interrupt to the system is actually an or combination of this bit and js7 js0 int. 3. interrupt implementation path is sele cted by the ints bit (register 0x74). 4. it is also possible to generate a software system interrupt by writing a 1 to this bit. js [7:4] int read write default 0 jsx logic is not interrupting clears jsx interrupt default 1 sx logic interrupted generates a software interrupt this bit always reports the logic st ate of js7 thru 4 detection logic. js [7:4] st jack state 0 no jack present js [7:4] st (ro) 1 jack detected this bit selects the operation mode for js2 and js3. js [3:2] md interrupt mode js [3:2] md 0 jack sense modejack sense state requires software polling default 1 interrupt modejack sense evet ns will generate interrupts
preliminary technical data AD1986 rev. 0 | page 41 of 52 register function this bit selects the audio interrupt implement ation path (for js4 to 7). this bit does not generate an interrupt, rather it steers the path of the generated interrupt. js4 to 7h interrupt modejs4 to 7 0 bit 0 slot 12 (modem interrupt) default js4C7h interrupt mode select 1 slot 6 valid bit (mic adc interrupt) x reserved default: 0 misc control bits 3 (register 0x7a) reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x7a misc control bits 3 jsinvb hpsel1 hpsel0 losel jsinva lvref 2 lvref1 lvref 0 x x x lohpen gpo mmix x x 0x0000 table 65. register function used in conjunction with the oms [2:0] (0x74 d10:08), ms (0x20 d08), and 2cmic (0x76 d06) bits to mix the microphone selector left/right channels. if the mmix bit is set, the 2cmic and ms bits are ignored. mmix function default 0 microphone channels are not mixed default 1 the left/right channels from the microphone selector are mixed mmix sets the state of the gpo pin gpo gpo function 0 gpo pin is at logic low (dv ss ) default 1 gpo pin is at logic high (dv dd ) lohpen enables the headphone drive on the line_out pins. disabling the headphone drive is the same as powering it down (see the pr6 bit (0x26 d14)). lohpen function 0 line_out headphone drive is disabled default 1 line_out headphone drive is enabled lvref [2:0] (line in vref_out) sets the voltage/state of the line_in vref_out signal. vref_ out is used to power microphone style devices plugged into the connected jack circuitry. the vref_out pin must be conne cted to both the left and righ t channels through external resistors to function properly. selections other than those defined are invalid and should not be programmed. line_in vref_out setting lvref [2:0] 5.0 av dd 3.3 v av dd 000 hi-z hi-z default 001 2.25 v 2.25 v 010 0v 0 v 100 3.70 v 2.25 v this bit allows the line_out output amplifiers to be driven by the mixer or the surround dacs. the main purpose for this is to allow swapping of the frontand surround channels to ma ke better use of the surr/hp_ou t output amplifiers. this bit should normally be used in tand em with the hpsel bit (see below). losel (line_out amplifiers input select) losel line_out select 0 line_out amplifiers are driven by the analog mixer outputs default 1 line_out amplifiers are driven by the surround dac sense_a: select the style of switches used on the audio jacks connected to sense a. jsinva jack sense invert jsinva jack sense invertsense_a 0 sense_a configured for normally- open (no) switches default 1 sense_a configured for normally-closed (nc) switches
AD1986 preliminary technical data rev. 0 | page 42 of 52 register function this bit allows the headphone power amps to be driven from the surround dacs, c/lfe dacs, or from the mixer outputs. hpsel [1:0] hp_out selection 00 outputs are driven by the mixer outputs default 01 outputs are driven by the surround dacs hpsel [1:0] (headphone amplifier input select) 1x outputs are driven by the c/lfe dacs sense_b: select the style of switches used on the audio jacks connected to sense b. jsinvb jack sense invertsense_b 0 jack_sense_b configured for normally- open (no) switches default jsinvb (jack sense invert) 1 jack_sense_b configured for normally- closed (nc) switches x reserved. default: 0 vendor id registers (register 0x7c to 0x7e) reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x7c vendor id 1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 0x4144 0x7e vendor id 2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 0x5378 table 66. register function s [7:0] this register is ascii encoded to a. f [7:0] this register is ascii encoded to d. t [7:0] this register is ascii encoded to s. rev [7:0] this register is set to 0x78, identifying the AD1986. codec class/revision register (register 0x60) reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x601 codec class/rev x x x cl4 cl3 cl2 cl1 cl0 rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 0x0002 table 67. register function default rv [7:0] (revision id: (ro)) these bits specify a device specific revision identifie r. the vendor chooses this value. zero is an acceptable value. this field should be viewed as a vendor defi ned extension to the codec id. this number changes with new codec stepping of the same codec id. this number will increment with each stepping/rev. of the codec chip. the AD1986 will return 0x00 from this register. this is a codec vendor specific field to define software compatibility for the codec. software reads this field together with codec vendor id (register 7cC0x7e) to determine vendor specific programming interface comp atibility. software can rely on vendor specific register behavior to be compatible am ong vendor codecs of the same class. 0x00 field not implemented cl [4:0] (codec compatibility class (ro)) 0x01-0x1f vendor specific compatibility class code x reserved. default: 0
preliminary technical data AD1986 rev. 0 | page 43 of 52 pci subsystem vendor id register (register 0x62, page 01) this register is only reset by power-on. it is used by the bios to store configuration information (per ac 97 revision 2.3 spe cification) and must not be reset by soft or hardware resets. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x621 pci svid pvi15 pvi14 pvi13 pvi12 pvi11 pvi10 pvi9 pvi8 pvi7 pvi6 pvi5 pvi4 pvi3 pv i2 pvi1 pvi0 0xffff table 68. register function pvi [15:0] pci sub system vendor id optional per ac 97 specificat ions, should be implemented as read/write on AD1986. this field provides the pci subsystem vendor id of the audio or modem suba ssembly vendor (i.e., cnr manufacturer, motherboard vendor). this is not the code c vendor pci vendor id or the ac 97 co ntroller pci vendor id. if data is not available it should return 0xffff. pci subsystem device id register (register 0x64, page 01) this register is only reset by power-on. it is used by the bi os to store configuration information (per ac97 v2.3 specificatio n) and must not be reset by soft or hardware resets. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x641 pci sid pi15 pi14 pi13 pi12 pi11 pi10 pi9 pi8 pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0 0xffff table 69. register function pi [15:0] (pci vendor id) optional per ac 97 specifications, shou ld be implemented as read/write on the AD1986. this field provides the pci subsystem id of the audio or modem subassembly (i.e., cnr mo del, motherboard sku). this is not the codec vendor pci id or the ac 97 controller pci id. inform ation in this field must be available, be cause the ac 97 controller reads when the codec ready is asserted in the ac link. if data is not available it should return ffffh. function select register (register 0x66, page 01) this register is used to select which function (analog i/o pins), information and i/o ( 0x 6801), and sense ( 0x 6a01) registers apply to it. the AD1986 associates fc = 0x 0 with surround functions and fc = 0x0 1 with front functions. these are changed in the AD1986 to align with the new device pin-out and to separate line_out functions. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x661 function select x x x x x x x x x x x fc3 fc2 fc1 fc0 t/r 0x0000
AD1986 preliminary technical data rev. 0 | page 44 of 52 table 70. register function t/r (fip or ring selection bit) this bit sets which jack cond uctor the sense value is measured from. soft ware will program the corresponding rng/tp selector bit together with the i/o number in bits fc [3:0]. once software programs the value and properly reads it back to confirm selection and implementation, it wi ll access the rest of the bits fields in the descriptor. mono inputs and outputs should report the relevant function and sense information when t/r is set to 0 (tip). the fip bit should report 0 (page 0x01, register 0x68, bit 0 reports no function information pr esent) when t/r is set to a 1 on a mono input or output. t/r function 0 tip (left channel) default 1 ring (right channel) these bits specify the type of audio function described by this page. these bits are read /write and represent current ac 97 revision 2.2 defined i/o capabilities. software will pr ogram the corresponding i/o numb er in this field together with the tip/ring selector bit t/r. once software programs the value and properly reads it back to confirm selection and implementation, it will access the rest of the bits fields in the descriptor. fc [3:0] function fc [3:0] function code bits 0x0 dac 1 (master out). maps to front dacs (l/r) default 0x1 dac 2 (aux out). maps to surround dacs (l/r) 0x2 dac 3 (c/lfe). maps to c/lfe dacs 0x3 s/p-dif out 0x4 phone in 0x5 mic_1 (mic select = 0) 0x6 mic_2 (mic select = 1) 0x7 line in 0x8 cd in 0x9 video in not supported on the AD1986 0xa aux in 0xb mono out 0xc headphone ut 0xdC0xf reserved x reserved. default: 0 information and i/o register (register 0x68, page 01) this address represents multiple registers (one for each supported function code (fc [3:0] bits ( 0x 66 d [04:01])). these values are only reset by power-on. it is used by the bios to store configuration information (per ac 97 revision 2.3 specifications) and must not be reset by soft or hardware resets. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x681 information and i/o g4 g3 g2 g1 g0 inv dl4 dl3 dl2 dl1 dl0 iv x x x fip 0xxxxx table 71. register function fip (ro) (function information present) codec default. when set to a 1, this bi t indicates that the g [4:0], inv, dl [4 :0] (in register 0x681), and st [2:0] (in register 0x6a1) bits are supported and are read/write capable. th is bit set to a 0 indicates that the g [4:0], inv, dl [4:0], a nd st [2:0] bits are not supported, and are read-only with a valu e of 0. mono inputs and outp uts should report the relevant function and sense information when t/r is set to 0 (tip). the fip bit should report 0 (page 0x01, register 0x68, bit 0 reports no function information present) when t/r is set to a 1 on a mo no input or output. fip function 0 function information not supported power-on default 1 function information supported
preliminary technical data AD1986 rev. 0 | page 45 of 52 register function indicates whether a sensing method is provided by the codec and if information field is valid. this field is updated by the codec. iv (information valid bit) iv function 0 after codec reset de-assertion, it indicates the code c does not provide sensing logic and this bit will be read-onl y. after a sense cycle is completed indicates that no information is provided on the sensing method. 1 after codec reset de-assertion, it indicates the codec provides sensing logic for this i/o and this bit is read/write. after clearing this bit by writing 1, when a sens e cycle is completed indicates that there is valid information in the remaining descriptor bi ts. writing 0 to this bit has no effect. dl [4:0] (buffer delays, read/write) a number representing a delay measuremen t for the input and output ch annels. the default value is the delay internal to the codec. the bios may add to this value the known delays external to the codec, such as for an external amplifier, logic, etc. software will use this value to accurately calculate audio stream position with respect to what is been reproduced or recorded. these values are in 20.83 micro second (1/48000 second) units. for output channels, this timing is from the end of ac link frame in which the sample is provided, until the time the analog signal appears at th e output pin. for input streams, this is from when the analog signal is pr esented at the pin until the representative sa mple is provided on the ac link. analog to analog paths are not considered in this measurement. the measurement is a typical measurement, at a 48 khz sample rate, with minimal in-codec processing (i.e., 3d effects are tur ned off.) an example of an audi o output delay is filter group delay and fifo or other sample buffers in the path. so when an audio pcm sample is written to the codec in an ac 97 frame it will be delayed before the o utput pin is updated to that value. dl [4:0] function 0x00 information not provided 0x01-0x1e buffer delay: 20.83 s per unit 0x1f reserved indicates that the codec presents a 180 degr ee phase shift to the signal. this bit is only reset by a power-on reset, since it is typically written by the system bios and is not reset by codec hard or soft resets as long as power remains applied to the codec. inv function 0 no phase shift inv (inversion bit, read/write, codec default) 1 signal is shifted by 180 from the source signal g [4:0] (gain bits (read/write)) the codec updates these bits with the gain value (db relative to level-out) in 1.5 dbv increments, not including the volume control gains. for example, if the volume gain is to 0 db, then the output pin should be at the 0 db level. any difference in the gain is reflected here. when relevant, the bios updates this bit to take into co nsideration external amplifiers or other external logic that it knows about. g [3:0] indicates the magnitude of the gain. g [4 ] indicates whether the value is a gain or attenuationessentially it is a sign bit. these bits are only reset by a power-on re set as they are typically written by the system bios and are not reset by codec hard or soft re sets as long as power remains applied to the codec. g4 g [3:0] gain/attenuation (db relative to level-out) 0 0000 0 db 0001 +1.5 db 0 ... +1.5 db g [3:0] 1111 +24.0 db 0001 ?1.5 db 1 ... ?1.5 db g [3:0] 1111 ?24.0 db x reserved default: 0
AD1986 preliminary technical data rev. 0 | page 46 of 52 sense register (register 0x6a, page 01) this address represents multiple registers (one for each supported function code (fc [3:0] bits ( 0x 66 d [04:01])). the st [2:0] bits are only reset by power-on. they are used by the bios to store configuration information (per ac 97 revision 2.3 specifications) a nd must not be reset by soft, hard or hardware resets. the remaining bits are the result of the last sense operation performed by the i mpedance sensing circuitry. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x6a1 sense register st2 st1 st0 s4 s3 s2 s1 s0 or1 or0 sr5 sr4 sr3 sr2 sr1 sr0 0xxxxx table 72. register function default sr [5:0] (ro) (sense result bits, ro) these bits are used to report a vendor specific fingerprint or value. (resistance, impedance, reactance, etc. used with the or bits which are the multiplying factor. default: 0 these bits indicate the order the sense result bits sr [5:0] are using. for example, if measuring resistance sr = 1/or = 11: the result is 1 k?. or [1:0] order value 00 10 0 sr bits indicate the actual impedance in ohms default 01 10 1 ssr bits indicate the impedance in ohms 10 10 10 2 sr bits indicate the impedance in ohms 100 or [1:0] (ro) (order bits) 11 10 3 ssr bits indicate the impedance in ohms 1,000 s [4:0] (ro) sensed bits meaning relates to the i/o being sensed as in put or output. read only. se nsed bits (when output sense cycle initiated). this field allows for the reporting of the type of output peripheral/device plugged in the jack. values specified below should be interrogated with th e sr [5:0] and or [1:0] for accurate reporting. s [4:0] sense value 0x00 data not valid. indicates that the reported value(s) is invalid 0x01 no connection. indicates that th ere are no connected devices default 0x02 indicates a specific fingerprint value for devices that are not specified or are unknown 0x03 speakers (8 ?) 0x04 speakers (4 ?) 0x05 powered speakers 0x06 stereo headphone 0x07 spdif out (electrical) 0x08 spdif out (tos) 0x09 mono headset (mono speaker left channel and mic. read functions 5 and 6 for matching microphone) 0x0a allows a vendor to report sensing other type of devices/peripherals. sr [5:0] together with or [1:0] provide informat ion regarding the type of device sensed 0x0bC0x0e reserved 0x0f unknown (use fingerprint) 0x10C0x1f reserved s [4:0] (ro) sensed bits (when input sense cycle initiated). th is field allows for the reporting of the type of input peripheral/device plugged in the jack. values specified below should be inte rrogated with the sr [5:0] and or [1:0] bits for accurate reporting. st [2:0] sense value 0x10 data not valid. indicates that the reported value(s) is invalid 0x11 no connection. indicates that th ere are no connected devices default 0x12 indicates a specific fingerprint value for devices that are not specified or are unknown 0x13 microphone (mono)
preliminary technical data AD1986 rev. 0 | page 47 of 52 register function default 0x14 microphone (stereo) 0x15 stereo line in (ce device attached) 0x16 mono line in (ce device attached) 0x17 spdif in (electrical) 0x18 spdif in (tos) 0x19 headset (mono speaker left channel and mic.) read functions 0 to 3 for matching dac out 0x1a allows a vendor to report sensing other types of devices/peripherals. sr [5:0] together with or [1:0] provide informat ion regarding the type of device sensed 0x1bC0x1e reserved 0x1f unknown (use fingerprint) st [2:0] (connector/jack location bits, read/write) this field describes the location of the jack in the system. this field is updated by the bios. this bits is only reset by a power-on reset as it is typically written by the system bios and is not reset by codec hard or soft resets as long as power remains applied to the codec. st [2:0] jack location 0x0 rear i/o panel power-on default 0x1 front panel 0x2 motherboard 0x3 dock/external 0x4C0x6 reserved 0x7 no connection/unused i/o
AD1986 preliminary technical data rev. 0 | page 48 of 52 jack presence detection the AD1986 uses two jack sense lines for presence detection on up to eight external jacks. these lines, combined with the device detection circuitry, enable software to determine whether there is a device plugged into the circuit and what type of device it is. with this feature, software can reconfigure jacks and amplifiers as necessary to insure proper audio operation. jack presence is detected using a resistor tree arrangement. up to four jacks can be sensed on a single sense line by using a different value resistance for each jack between the sense line and ground (av ss ). each sense line must have a single 2.49k 1% resistor connected between the sense line and av dd . the specific resistor values for each jack are shown in table 73. one percent tolerance resistors should be used for all jack presence circuitry to insure accurate detection. audio jack styles (nc/no) the jack sense lines on the AD1986 can be programmed for use with normally-open (no) or normally closed (nc) switch types. current standard stereo audio jacks have wrap-back pins that are normally closed. new audio jacks use isolated, normally open switches, which are required for resistive ladder jack presence detection. each sense group (a or b) must have the same style of jack for presence detection to function correctly. however, the group (a or b) sense type can be programmed separately to accommodate systems with different styles of jacks on the front versus rear panel. the AD1986 defaults to the isolated, normally open switch types on power up. the jack sense style for sense_a is controlled by the jsinva bit (register. 0x 7a d11). the jack sense style for sense_b is controlled by the jsinvb bit (register 0x 7a d15). writing a 1 to these bits will configure the corresponding sense circuit for normally closed instead of normally open switch types. wrap-back jacks cannot be used in microphone-capable cir- cuits. for this reason isolated switches are recommended. the codec defaults to sensing no style switches and this method is preferred. normally-open switches if a connection is not present , do not install the sense resistor pertaining to that connection. if a connection is present, but there is no related switch (such as an internal connection) , i nstall the sense resistor pertaining to that connection. normally closed switches connections capable of mic bias require isolated switches to function correctly. when using normally closed, wrap-back switches, the jack resistor must be split into two values. one value connects the sense line to the jack switch and the other connects the related audio connection to av ss . the total resistance (sense line to av ss ) must equal the value specified in table 73. if a connection is not present , install the sense resistors pertaining to that connection. if a connection is present, but there is no related switch (such as an internal connection) , do not install the sense resistors pertaining to that connection. table 73. jack sense mapping jack_sense_a jack_sense_b resister (1% tolerance) mnemoni c jack js mnemonic jack js 4.99k d js7 line out h js0 10.0k line in c js4 c/lfe g js3 20.0k mic_1/2 b js5 surround f js2 40.2k hp_out a js1 aux in e js6
preliminary t echnical data AD1986 r e v . 0 | p a ge 49 of 5 2 microphone selection/mixing g mic 1 center line in l mic 2 lfe line in r g mic left mic righ t mic select: oms[2:0] 0x74 d10-d08 def=000 (mic 1/2) 000-mic 1/2 001-line in 01x-c/lfe 100-mic+c/lfe 101-mic+line in 110-c/lfe+line in 111-mic+c/lfe+line nid: 0x0f nid: 0x27 nid: 0x28 nid: 0x29 nid: 0x2a nid: 0x2b nid: 0x11 mic boost: ac97 m20 0x0e d6 def=0 mgb[1:0] 0x76 d[1:0] def=00 mgb m20 [1:0] gain 0 x x 0db 1 0 0 +20db 1 0 1 +10db 1 1 0 +30db 1 1 1 reserved azalia mgbl[1:0] 0x70 d[1:0] mgbr[1:0} 0x70 d[14:13] mgbl/r [1:0] gain 00 0db 01 +10db 10 +20db 11 +30db mic swap: ac97 ms 0x20 d08 def=0 2cmic 0x76 d06 def=0 mmix 0x7a d02 def=0 azalia mswp[2:0] 0x7a d02:00 mmix 2cmic ms mswp2 mswp1 mswp0 right left 0 0 0 mic 1 mic 1 0 0 1 mic 2 mic 2 0 1 0 mic 2 mic 1 0 1 1 mic 1 mic 2 1 x x mic 1+2 mic 1+2 f i gure 10. m i c r op h o ne s e lec t ion / m i x i ng block d i ag r a m
AD1986 preliminary t echnical data r e v . 0 | p a ge 50 of 5 2 outline dimensions top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc f i g u re 11. 4 8 -l ead l o w p r of i l e q u ad f l at p a ckag e [l qf p ] (st - 48) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option AD1986jstz 1 0c to +70c 48-lead lqfp, tray st-48 AD1986jstz 1 -r eel 0c to +70c 48-lead lqfp, r eel st-48 AD1986bstz 1 C40c to +85c 48-lead lqfp, tray st-48 AD1986bstz 1 -r eel C40c to +85c 48-lead lqfp, r eel st-48 1 z = pb-free part.
preliminary technical data AD1986 rev. 0 | page 51 of 52 notes
AD1986 preliminary t echnical data r e v . 0 | p a ge 52 of 5 2 notes ? 20 04 a n a l o g de v i ces, i n c . a l l rig h ts r e s e r v e d . t r ad em a r k s and reg i ste r e d tr ad em a r k s a r e t h e p r op e r t y of t h e i r resp e c tive ow ne r s . d04785-0 - 10/0 4 (0)

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